FR2565447A1 - Device for digitising a video image and image digitising and displaying system - Google Patents

Abstract

Device for digitising a video image and digitising and displaying system containing the said device. The digitising device comprises a sampling means 10 receiving a video signal and delivering a clock signal at the sampling frequency, this signal being resynchronised with each line synchronising pulse of the video signal, an analog/digital converter 14 delivering a digitised video signal and a means of extraction 46 for extracting a digitised image from the digitised video signal. The system furthermore comprises a digital/analog converter 48, a display means 50 and an image processing calculator 52.

Description

DEVICE FOR DIGITIZING A VIDEO IMAGE AND
SYSTEM FOR SCANNING AND VIEWING A
PICTURE
The present invention relates to a device for digitizing a video image. This device allows real-time acquisition of a digital image from an interlaced or non-interlaced scanning video signal. The invention applies in particular to the medical field of digital tradiology, angiography), in robotics and industrial automation ( automatic sorting of parts, quality control, control of component insertion) in non-destructive control (weld control, aging) or other
The subject of the invention is also a system comprising said device for digitizing a video image and to which it is associated means for viewing the digital image being acquired or a stored image. This has significant advantages, especially in medical use.

 The video signal to be digitized is delivered by a video camera. In known digitizing devices, the video camera is synchronized by a scanning synchronization means which is controlled by the digitizing device. This makes it possible to simplify the digitization of the video signal, the rhythm of which is then perfectly known, but this however requires the use of a synchronizable video camera.

 This also assumes that the scanning synchronization signal delivered by the digitizing device is compatible with the video camera used. In practice, this results in a lack of flexibility, a particular camera having to be used with a particular digitizing device.

 An object of the invention is to be able to couple any video image source, synchronizable or not, with a digitizing device. The video image source can then be in particular a non-synchronizable video camera or a video recorder. To achieve this object, the invention provides a device for digitizing a video image which does not control the scanning synchronization means of the video image source.

 It is clear that this complicates the digitization of the video signal whose synchronization is unknown to the digitizing device. In addition, the phase of the video signal synchronization component can fluctuate over time. This is particularly the case if the video image source is a video recorder which generally has significant crying.

 To digitize the video signal, it is therefore necessary to extract the synchronization signal from the received video signal in real time and to develop a sampling signal from said synchronization signal. The subject of the invention is such a device for digitizing a video image.

Specifically, the invention has for object a device for digitizing a video image comprising: - a sampling means receiving an image signal
video and delivering a clock signal to the frequency
sampling signal, this clock signal being resyn
chronized on each synchronization pulse of
video image signal line, - an analog-digital converter receiving the
video image signal on its data input and the
clock signal on its sample command input
the said analog-digital converter
delivering a digitized signal from the video signal, - an extraction means for extracting from the digital signal
se a scanned image by eliminating samples
Ions of the digitized signal corresponding to the synchroni
video signal.

According to a preferred embodiment, the sampling means of the device of the invention comprises in series: - a separation means receiving the video signal and
delivering the synchronization component of said if
general video, - a processing means producing a clock signal
at the Line synchronization frequency, - a frequency multiplier delivering a signal
clock resynchronized on each syn pulse
video image signal line timing.

 According to a preferred embodiment, the extraction means of the device of the invention comprises an image memory, the data input of which is connected to the analog-digital converter and an acquisition means receiving as input the signal d clock at the sampling frequency and the line synchronization signal of the video signal and delivering an addressing signal to the image memory.

The subject of the invention is also a system for digitizing and displaying an image comprising - a digitizing device, - a digital-analog converter whose input
data is connected to the converter output
analog-digital and whose control input re
receives the video signal synchronization signal, - a display means receiving the video signal
delivered by the digital-analog converter,
The invention finally relates to an image processing system comprising: - a digitization device, - a digital-analog converter whose input
data is connected to the converter output
analog-digital and whose control input
receives the video signal synchronization signal, - a display means receiving the video signal
delivered by the digital-analog converter, - a computer connected to the image memory by an AC
Direct access to memory (ADM or in English DMA)
The characteristics and advantages of the invention will emerge more clearly from the description which follows, given by way of illustration but not limitation, with reference to the annexed drawings in which:
FIG. 1 is a block table of the device for digitizing a video image of the invention,
FIG. 2 illustrates an embodiment of the sampling means of the device for digitizing a video image of the invention,
FIG. 3 is a timing diagram of the signals produced by each of the means of FIG. 2,
FIG. 4 illustrates an embodiment of the acquisition means,
FIGS. 5 and 6 are timing diagrams of the significant signals of the acquisition means of FIG. 4,
- Figure 7 is a block table of an image processing system comprising a device for digitizing a video image, a device for storing said image, a device for viewing a video image from the image being acquired or the stored image and a processing device,
FIG. 8 represents a circuit for controlling the operating mode of the system of FIG. 7.

 FIG. 1 shows a synoptic table of the device for digitizing a video image of the invention. This device 2 is associated with an image capture means 4 comprising a video camera 6 and a scanning synchronization means 8.

 The scanning device may use an unsynchronized video camera.

 However, the mathematical processing operations involving several digitized images require a point-to-point correspondence between any two digitized images. This condition leads, if working in interlaced scanning, to use only even frames or only odd frames, the video camera then operating at a rate of 25 frames per second.

 In order not to have to distinguish between even and odd fields, we prefer to choose a non-interlaced scanning operation which also offers the advantage of a frame rate of 50 images per second and does not change the definition of the scanned image. .

 The non-interlaced scanning at 50 images per second is obtained by the synchronization of the video camera 6 by means of a quartz clock followed by a divider chain and circuits for shaping the synchronization pulses.

 It is important to note that this part is completely separate from the digitization device and becomes useless as soon as one has a video signal in non-interlaced scanning or that one accepts to work in interlaced scanning at 25 frames per second. by discriminating between even and odd frames.

 The device 2 of the invention mainly comprises a sampling means 10 receiving the video signal 12 delivered by the video camera 6, an analog to digital converter 14 receiving said video signal and the sampling of which is controlled by the sampling means 10 and extraction means 46 for extracting a digitized image from the digitized video signal supplied by the analog-digital converter 14.

 According to the invention, the sampling means 10 extracts the synchronization signal from the video signal 12. It uses this signal to generate a clock signal at the sampling frequency, said signal being resynhronized at the start of each line d image with the synchronization signal extracted from the video signal.

 According to a preferred embodiment, the sampling means 10 comprises in series a separation means 16 for extracting the synchronization signal from the video signal, a processing means 18 producing a clock signal at the line synchronization frequency of the video signal and a frequency multiplier 20 delivering a pulse signal at the sampling frequency.

 The extraction means 46 comprises an image memory 42 the access to which is controlled by an acquisition means 44. The data bus of the image memory 42 is connected to the data bus of the logic-to-digital converter The acquisition means increments the addresses of the image memory. It delivers a write signal to the image memory as a function of the clock signal delivered by the frequency multiplier 20 and the line synchronization signal of the video signal delivered by the separation means 16. The last signal allows 'inhibit the write signal and block the increment of addresses when the digital sample delivered by the analog-digital converter corresponds to a part of the video signal synchronization and not to a useful part.

 FIG. 2 shows an embodiment of the sampling means 10. The timing diagram of FIG. 3 represents the significant signals of this sampling means.

 The separation means 16 receives the video signal S1. Each image frame comprises a preamble P for image synchronization, a registration signal R and a series of line signals L. Each line signal comprises a synchronization pulse followed by an analog signal representative of the gray level of The image line read. The preamble P has a length equal to approximately five lines and the registration signal R a length equal to approximately twenty lines.

 The separation means 16 extracts the synchronization of the video signal S2. This separation means 16 comprises a differential amplifier 22 mounted as an inverter which forms a buffer and the output of which is connected to the inverting input of a fast comparator 24.

A constant potential is applied to the non-inverting input of comparator 24 which thus forms a thresholding means.

 The signal S2 delivered by the separation means 16 is shown on the timing diagram of FIG. 3. This signal is a binary signal which contains the line synchronization pulses. This signal is not exactly a clock signal because iL lacks pulses during the preamble.

 These missing pulses will be added by the processing means 18 in order to develop a clock signal from which it will be possible to produce a sampling signal.

 The processing means 18 comprises a first monostable flip-flop 26, an OR gate 28 whose input is connected to the output of the first monostable flip-flop 26, a second monostable flip-flop 30 whose input is connected to the output of the OR gate 28 and a third monostable rocker 32 whose input is connected to the output of the second monostable rocker 30 and whose inverting output is connected to a second input of the OR gate 28.

 The first monostable flip-flop 26 has a time constant equal to the duration of the line synchronization pulses. This monostable flip-flop 26 therefore makes it possible to suppress the image synchronization pulse, that is to say the preamble in the signal S2.

 Monostable flip-flop 30 has a time constant equal to the duration of the line synchronization pulses and Monostable flip-flop 32 has a time constant almost equal to the period of line synchronization pulses. These two monostable flip-flops 30, 32 therefore constitute a multivibrator having a frequency practically equal to the frequency of the line synchronization pulses. This arrangement makes it possible to deliver at the output of the monostable flip-flop 30 a signal S3 in which line synchronization pulses have been added in place of the preamble of the signal S2.

 The processing means 18 operates as follows. When the signal S2 has pulses at the line synchronization frequency, the output of the monostable flip-flop 32, whose time constant is slightly greater than the period of the line synchronization pulses, is kept low. The signal S3 delivered by the monostable flip-flop 30 is therefore equal in this case to the signal S2. On the contrary, when the processing means 18 receives the preamble part of the signal S2, the monostable flip-flop 32 changes state since it is not reactivated after a duration equal to one line. Its output therefore goes high, which activates the monostable flip-flop 30. This adds a pulse in the output signal S3 and reactivates the monostable flip-flop 32. The cycle is repeated throughout the preamble part of the signal S2.

 The processing means 18 therefore delivers a signal S3 as shown in the timing diagram of FIG. 3. In this signal, the large single pulse of the preamble of the signal S2 has been replaced by line synchronization pulses.

 The signal S3 is received by the frequency multiplier 20. This includes a voltage controllable oscillator 34 (O.C.T.) which delivers a clock signal at the selected sampling frequency. This signal is phase locked to signal S3.

This synchronization is achieved by a phase-locked loop comprising a frequency divider 36 whose input is connected to the output of
OCT 34, a phase comparator 38 receiving on an input the signal S3 and on another input The signal delivered by the frequency divider 36, and a low-pass filter 40 whose input is connected to the output of the phase comparator 38 and whose output delivers an error signal t controlling the OCT 34. The division ratio of the divider 36 corresponds to the ratio of the frequencies of the sampling signal delivered by the OCT 34 and of the signal S3 The divider assembly 36 and phase comparator 38 can in particular be produced using a single integrated circuit such as the circuit
HEF 4750 of ... This circuit has the advantage of having a programmable division ratio.

 The sampling signal 54 delivered by the frequency multiplier 20 is therefore a signal which is synchronized for each line, with a line start pulse of the video signal. This is important because the means of synchronization of the image capture means Since video is not slaved to the digitizing device, the frequency stability of the line synchronization pulses may not be very great.

In order for the signal digitized by the analog-digital converter of the device of the invention to effectively sample each line at the same times relative to the start of the line signal, the sampling pulses must be reset to the synchronization pulse of this line. This explains the use of a phase locked loop in the frequency multiplier 20.

 It should also be noted that the sampling means could not function if the signal S2 was directly applied to the frequency multiplier 20. In fact, in this case, the phase-locked loop would unlock during the preamble during which the signal S2 is pulse free.

Relocking the loop requires at best 4 ms after the Line synchronization pulses reappear. In this case, therefore, at least 4 ms of sampling is lost on an image which lasts approximately 20 ms.

This defect is not admissible. This is remedied by the processing means 18 which adds line synchronization pulses in place of the preamble of the signal S2.

FIG. 4 shows an embodiment of the acquisition means 46. which stores the captured image. This means receives as input the synchronization signal S2 delivered by the separation means 16 and the clock signal at the sampling frequency S4 delivered by the frequency multiplier 20. This means produces a sequencing signal which is used after processing , for
memory addressing and memory write validation.

The acquisition means of Figure 4 allows
The memorization of a digital image of 256x256 points. The modifications to be made to this circuit to memorize digital images of different size are minor. They essentially relate to the counters 64 to 70 and the clock signals of the flip-flops 60 and 72. These modifications are easily achievable by those skilled in the art.

The acquisition means 46 comprises as input a monostable flip-flop 48 whose time constant is slightly greater than the duration between two line synchronization pulses. This monostable flip-flop receives the signal S2 delivered by the support means 16 of the digitizing device. The inverting output of this monostable flip-flop 48 is connected to the clock input H of a flip-flop 50 of type D, of which
The entrance is kept high. The inverting output Q of this flip-flop 50 is connected to the reset input RESET of a counter 50 which receives on its counting input CUP the signal 52 A flip-flop 54 of type D whose data input D is maintained at the high level receives on its clock input H the retaining signal RE of the counter 52. The non-inverting output of this flip-flop 54 is connected to one of the inputs of a NON ET56 gate.

This gate also receives the signal S4 delivered by the frequency multiplier 20, a signal
J for validating the sampling on a line of the image and a signal F for validating the sampling of an image. The signal delivered by the NAND gate 56 constitutes, near the sign, the signal for addressing the image memory 42 and for commanding writing to this memory. A NAND gate 58 mounted in inverter restores the sign of this signal.

The signal J is produced by the inverting output Q of a flip-flop 60 of type D whose input of
data is kept high. The reset reset input of this flip-flop is controlled by the inverting output of a monostable flip-flop 62 whose time constant is of the order of magnitude of the duration of a line synchronization pulse.

This monostable flip-flop 62 receives the signal as an input and is triggered on the rising edge of this sign.

 The signal delivered by the inverting output of gate 56 constitutes a clock signal to increment four counters 64, 66, 68 and 70. Each of these counters is a four-bit counter. They are interconnected in a known manner so as to constitute a counter with sixteen bits. These sixteen outputs make it possible to define the 256 × 256 addresses of the image memory. Note that the clock signal of the flip-flop 60 is constituted by the retaining signal RE of the counter 66.

 On the other hand, the retaining signal RE of the counter 70 constitutes the clock signal of a flip-flop 72 of type D, the input of which is kept high.

The inverting output Q of this flip-flop delivers the signal F, on the one hand to the AND gate 56, and on the other hand, to a monostable flip-flop 74 whose time constant is of the order of magnitude of the duration of a line synchronization pulse. The inverting output of this monostable flip-flop 74 is connected to the reset reset inputs of flip-flops 50 and 54.

 The circuit of FIG. 4 finally comprises a flip-flop 76 of type D whose data entry is maintained in the high state. The reset input RESET of this flip-flop is connected to the non-inverting output of the monostable flip-flop 48. This flip-flop receives on its clock input H the signal delivered by your gate 56.

Its non-inverting output Q is connected to the inputs of
reset to zero of counters 64, 66, 68 and 70.

 We will now explain the operation of this circuit with reference to FIGS. 5 and 6 which respectively represent signals at the image level and signals at the line level of the video signal.

 FIG. 5 shows the synchronization signal S2 produced by the separation means 16 of the digitizing device. The number of line synchronization pulses has been given for an image of this signal. There are 313 line synchronization pulses in an image of which approximately 290 actually correspond to a line of the video image, the first 20 line synchronization pulses not being followed by an analog signal, but only used for signal synchronization.

 A first function of the circuit of FIG. 4 is therefore to select 256 lines from the 290 image lines of the video signal. The solution followed here is to digitize the 256 central lines, approximately lines 32 to 288.

This is achieved in the following manner. The start of image in the signal S2 is detected by the monostable flip-flop 48 whose time constant is slightly greater than the duration between two line synchronization pulses. This monostable flip-flop delivers on its inverting output the signal A shown in FIG. 5. The flip-flop 50 receives this signal A on its clock input and therefore delivers a signal B which blocks the resetting of the counter 52. The latter then begins counting the pulses of signal S2 and deliver a carry signal C which goes high when the number of pulses received reaches a predetermined value, equal to 32 in FIG. 5. During this counting, the non-inverting output of the flip-flop 54 is at low level (it was reset at the end of
the digitization of the last image according to a process which will be described in the following). This signal, denoted D, returns to the high level when there is a hold in the counter. It is reset to Low when 256 image lines have been stored.

 The counting of stored lines is done as follows. When an image start is detected by monostable flip-flop 48, flip-flop 76 resets the memory addressing counters 64, 66, 68 and 70 as well as flip-flop 72. For each new image point memorized, The counters are incremented.

The signal E connected to the retaining pin RE of the counter 70 therefore goes high when 256 × 256 dots of image have been stored. The rising edge of this signal E therefore indicates that 256 image lines have been stored. This change of state of the signal E switches the signal F to the 1st level low, which therefore comes, on the one hand, to close the door 56 and on the other hand, to reset the flip-flops 50 and 54 by means of monostable scale 74.

 On the timing diagram of FIG. 5, the rising edge of the signal E results in the switching of the signal F which itself induces a pulse at the low level of the output signal G of the monostable flip-flop 74 which controls the resetting of the signals B and D.

 The clock signal S4 therefore crosses the gate 56 only when the signal D is in the high state.

This allows sampling for 256 lines of the video image. However, during this interval, the video signal comprises a useful part, which is to be digitized and stored, and a useless part constituted by the line synchronization pulses. The signal J is precisely produced so as to block the signal S4 during the useless part of the video signal.

 The mode of production of this signal J will be indicated with reference to FIG. 4 and with reference to the timing diagram of FIG. 6.

FIG. 6 shows the video signal S3 to be digitized and the synchronization signal of
Line S2 extracted from this signal S3.

 In order for the digital image obtained by the digitizing device to correspond to the analog image of the signal S3, it is only necessary to sample the useful part (analog) of the signal S3. In known digitizing devices, this precaution is not always taken and Sampling does not memorize not only the image signal but also the synchronization signals. The acquisition means of FIG. 4 on the contrary makes it possible to sample only the useful part of the video signal. For this, we will produce a signal J which validates the sampling signal only in the analog part of the video signal, this 256 times per video line. These 256 sampling pulses are equidistant and are preferably centered on a Line from Inage video.

This validation signal is the signal J. To obtain it, the signal S2 is shifted by means of the monostable flip-flop 62. The time constant of this flip-flop is chosen so that the start of sampling takes place at an instant such that Sampling is centered on the analog part of a line of the video signal. The signal I delivered by the monostable flip-flop 62 is applied to the reset input RESET of flip-flop 60 whose inverting output delivers the signal J. This therefore goes high at the end of the pulse delivered by monostable scale 62
The sampling of the video signal line then begins. When 256 image points have been memorized, The retaining signal RE of the counter 66 goes high, which induces a signal switching
J and finish sampling the line.

 In FIGS. 5 and 6 The signals H and SE respectively represent the sampling signal at the level of an image and at the level of a line of the video signal.

 FIG. 7 shows a synoptic table of an image processing system which allows both the digitization of a video image, the visualization of an image in the course of acquisition or the visualization of a digital image processed by a computer. The device for digitizing a video image included in this system is in accordance with the invention.

 This system comprises an image capture means 4 consisting of a video camera 6 and possibly a scan synchronization means 8. The signal delivered by this image capture means is received in a conforming digitizing device 2 to the invention.

 This device comprises in series a separation means 16 for extracting the synchronization signal from the video signal, a processing means 18 for producing a clock signal at the line synchronization frequency, a frequency multiplier 20 producing a signal clock at your standardization frequency, said signal being resynchronized on each line synchronization pulse of the video signal.

This clock signal is applied to the control input of the analog-digital converter 14 which receives the video signal on its data input. The analog-digital converter 14 outputs a digitized video signal.

 An image memory 42, the addressing of which is controlled by an acquisition means 44 receiving as input the clock signal delivered by the frequency multiplier 20 and the line synchronization signal delivered by the separation means 16 makes it possible to load into the image memory 42 a digital image extracted from the digitized video signal delivered by the analog-digital converter 14.

 This digitizing device of the invention, of which FIGS. 1 to 6 illustrate an embodiment, constitutes one of the three functions of the system of FIG. 7.

 Another interesting function performed by this system is the visualization of the image being acquired by the digitizing device. This function is obtained by the use of a digital-analog converter 48 whose data input is connected to the output of the analog-digital converter 14 and whose control input receives the line synchronization signal delivered by the means separation device 16. The analog signal delivered by this analog-digital converter 48 is applied to a display means 50.

 This function allows viewing the digital image being acquired in the image memory 42 and not only the video image delivered by the camera 6. This control of the image being acquired is not possible with known devices.

In these, the image can only be viewed after its acquisition. The characteristic magnitudes of the image (brightness, contrast) are therefore adjusted by trial and error by memorizing and viewing successively several images until a correct digital image is obtained. With the system of the invention, on the contrary, the result of a modification of the setting of
The brightness or contrast appears in real time, which considerably simplifies the capture of an image.

 The third function performed by the system of FIG. 7 is a function for processing a digital image. This function is performed by a computer 52 connected to the memory 42 by a DMA channel.

 The calculator can in particular carry out the following treatments: - text overlay in the image, - copy of the image on a graphic printer, - histogram, - contrast enhancement, - automatic contour tracking, - transformation of the image into pseudo-colors.

 The system can operate in three modes: memoryless, write and read.

 In the memoryless mode, the inputs and outputs of all the memories are at high impedance.

The digital-to-analog converter 48 receives the digitized video signal from the analog-to-digital converter 14 and mixes there the synchronization signal of
Delivered by the separation means 16. This therefore allows the visualization of the spun image in real time.

 In the write operation, the operation is identical to the previous operation but moreover the image memory 42 receives the write and selection pulses WR and CS.

In read operation, the output of the analog-digital converter 14 is set to high impedance and the image memory 42 is validated in
Reading. The image displayed by the display means 50 comes from the image memory 42.

 FIG. 8 represents a diagram of a circuit making it possible to choose one of the three operating modes of the system.

This circuit includes an inverter 76 receiving as input the sampling signal SEs a door
NO AND 78 with three inputs, one connected to the output of
the inverter 76, another connected to ground through a switch 80, a third connected to the inverting output Q of a flip-flop 82 of type D.

 The data entry D of this flip-flop is kept high; its clock input H receives the signal A which presents a rising edge at each start of image of the video signal. This signal is delivered by the monostable flip-flop 48 of the circuit of FIG. 4. The reset input RAZ of this flip-flop 82 is controlled by the non-inverting output Q of a flip-flop 84 of type J-K. Entries J and K of this rocker are maintained at the high level. The clock input H of this flip-flop 84 is connected to a push button 86. The signal received on the clock input H of flip-flop 84 is at the high level; it goes low When the push button 86 is activated.

The signals produced by this circuit are - a STROMBE validation signal from the digital converter
rique-analog, - a signal WR which positions the image memory 42 in
write when low and read
when it is high, - an OE validation signal (in English "output ena
ble ") of data output from the image memory 42, - and a CE signal (in English" chip enable ")
dd analog to digital converter.

 The circuit works as follows.

The switch 80 allows the contents of the image memory 42 to be saved. When it is open, the signal 7R is at the high level and it is impossible to write to the image memory 42. The stored image is therefore confined.

 On the other hand, the associated push button 86 and the rocker 84 constitute a bistable rocker.

The output signal Q of the flip-flop 84 therefore changes state at each activation of the push button 86.

 In one state, the analog-to-digital converter is active (signal CE at the low level) and the image reconstructed on the viewing means 50 then comes from the video camera. In this state, the image memory 42 is loaded or not with the image scanned according to the state of the switch 80.

 In the other state, the analog to digital converter is at rest. On the other hand, the signal for validation of memory output (signaL Xt) is active and the write impulses WR are inhibited. The system therefore reads the content of the damage memory 42 and restores the image on the display means 50.

When passing from the first state to the other,
The memorization of the current image is continued until the end of this image, the change of state being synchronized with the start of a video image by the signal A applied to the clock input H of La bascu
The 82.

Claims (10)

 1. Device for digitizing a video image, characterized in that it comprises: - a sampling means (10) receiving a signal  video image and delivering a clock signal to the  sampling frequency, this clock signal  being resynchronized on each sync pulse  Line definition of the video image signal, - an analog-digital converter (14) receiving  The video image signal on its data input and  The clock signal on its control input  sampling, said analog converter  shit (14) dice Delivering a digitized signal  video, - an extraction means (46) for extracting the signal  scanned a scanned image by eliminating  samples of the digitized signal corresponding to the  video signal synchronization.  2. Device according to claim 1, characterized in that the sampling means (10) comprises in series: - a separation means (16) receiving the video signal  and delivering the synchronization component of said  video signal, - a processing means (18) generating a signal  clock at Line synchronization frequency, - a frequency multiplier (20) delivering if  clock signal resynchronized on each pulse of  Line synchronization of the video image signal.  3. Device according to claim 2, ca racterized in that the separation means (16) comprises a thresholding means (24).  4. Device according to claim 2, ca racterized in that the processing means (18) comprises a first monostable flip-flop (26), delivering pulses whose time constant is equal to the duration of the signal line synchronization pulses video, an OR gate (28) whose input is connected to the output of said first monostable flip-flop, a second monostable flip-flop (30) similar to the first monostable flip-flop, and whose input is linked to the output of the OR gate , and a third monostable flip-flop (32) whose input is connected to the output of the second monostable flip-flop and the inverting output to another input of the OR gate, said third monostable flip-flop having a time constant equal to the duration between two consecutive line synchronization pulses of the video signal.  5. Device according to claim 2, ca characterized in that the frequency multiplier (20) comprises a voltage controllable oscillator (34) delivering a clock signal at the sampling frequency, a divider (36) receiving the signal clock and delivering a signal at the line synchronization frequency, a phase comparator (38) receiving the signal delivered by the divider and the signal delivered by the processing means and delivering through a low-pass filter (40) an error signal () for controlling the oscillator (34).  6. Device according to claim 1, ca characterized in that the extraction means (46) comprises a memory (42), the data input of which is connected to the analog-digital converter (14) and an acquisition means ( 44) receiving the clock signal as input Houses the sampling frequency and the line synchronization signal of the video signal and delivers an addressing signal to the memory (42).  7. Device according to claim 6, ca characterized in that the acquisition means (44) comprises means for selecting N consecutive tignes from among the F lines of a video image <N <P), and means for sampling Q points per Line selected.  8. Device according to claim 7, characterized in that the acquisition means (44) further comprises means for limiting the sampling of each line to the useful part of the video signal.  9. An image digitization and display system characterized in that it comprises: - a digitizing device, - a digital-to-analog converter (48) including  The control input receives the synchronization signal  tion of the video signal, - a means of connecting the convertor's data bus  digital-analog sor (48) to the data bus of the  analog-to-digital converter (14) or to the bus  image memory data (42), a display means (50) receiving the signal vi  deo delivered by the digital-analog converter  that, the digitizing device being in accordance with any one of claims 1 to 8.  10. An image digitization and display system according to claim 9, characterized in that it further comprises an image processing calculator (52) connected to the image memory (42) by a channel d 'direct access to memory.