FR2535130A1 - ANALOG-DIGITAL AND DIGITAL-ANALOG CONVERTER - Google Patents

Abstract

A. THE INVENTION RELATES TO AN ENCODING AND DECODING SYSTEM FOR ENCODING AN ANALOGUE SIGNAL INTO DIGITAL FORM AND RECONSTRUCTING THE ANALOGUE SIGNAL FROM ITS ENCODED DIGITAL FORM. B. THE SYSTEM APPLIES TO AN ADVANCED FIXED DELTA MODULATION TECHNIQUE ALLOWING THE PRODUCTION OF WEIGHTED BINARY SIGNALS BASED ON A COMPARISON BETWEEN THE VALUE OF THE ANALOGUE SIGNAL DURING EACH OF A PREDETERMINED NUMBER OF PREDETERMINAL INTERVALS OF TIME WITH A NUMBER OF THESE VALUES DURING PREVIOUS INTERVALS. THIS TECHNIQUE IS ASSOCIATED WITH COMPRESSION-EXPANSION TECHNIQUES TO ALLOW TO MODIFY THE FIXED STEP SIZE OF THE OUTPUT OF THE FIXED DELTA MODULATION. THIS HELPS AVOID QUANTIFICATION AND NOISE ERRORS, ENSURES A GREATER DYNAMIC AREA AND REDUCES NOISE AND DEFORMATION. C. APPLICATION: CONVERSION INTO DIGITAL FORM OF AN ANALOGUE SIGNAL AND REPRODUCTION OF THE ANALOGUE SIGNAL FROM ITS DIGITAL FORM.

Description

The present invention relates to analogue conversion in

  digital and digital analog signals.

  Since the advent of digital signal processing, the focus has been on converting (i.e., encoding) analog information signals (ie, video or audio signals). ) in digital format to enable the processing and / or recording of digitally encoded signals and the conversion (ie decoding) of signals processed by

  digital channel to give them an analog format.

  An analog-to-digital converter used for this purpose uses a technique of pulse code modulation (PCM) Potur c-e type of modulation, a binary output signal

  eat g 6 N 6 r 6 which has a value proportional to the amplitude of the

  analog input signal during a discrete time interval predefined Standard models tend to establish

  netted coeds in 14-bit and 16-bit binary This type of

  is not only expensive but also tends to be

  of the bit errors in the transmission medium.

  It follows that PCM devices of the prior art typically use complicated error correction codes when recording the information signal.

  form (for example, when recording on a machine)

  Additional bits containing information about codes are usually recorded on the tape.

  to correct errors when reproducing

  This entails "extra" information that must be

  This supplement may represent 40% of the total

  heights 6 of the recorded information.

  A technique that has been implemented, called modulation

  delta, is less sensitive to bit gaps in the systems.

  my die midulaion delta, the digitally encoded signal is in fact constituted by a binary bit stream, each having one of x binary values (i.e., a value being "1" logical one leveled high "while the other is a logical "O" or "low") and represents the slope of each segment of the araleogous signal during a predetermined discrete time interval

  compared to the value of the analog signal during

  previous bit time Bit "1" means that the slope of the analog input is positive during this time interval while the "O" bit means that the slope of the analog signal is negative during this time interval. a digitally encoded signal, the decoder reconstructs the analog signal by increasing the amplitude of its output by a predetermined amount (called "step size") in response to bit "1" of the digitally encoded signal stream and (2) by decreasing the amplitude of its output by a determined amount in response to

  an "O" bit of the digital encoded signal stream The preponderance

  ratio of bits "1" and "O" in the digital signal stream.

  indicates whether the analog signal is rising, falling or

  constant, more precisely, a series of consecutive bits

  "1" indicates a continuously increasing analog signal for the time intervals represented by the bits,

  a series of consecutive bits at the "O" level indicates a decrease

  continuous operation of the analog signal during

  time represented by bits and bits "O" and "1" alternately

  nance indicate an analog signal of constant amplitude

  during the time intervals represented by the bits.

  When encoding an analog signal using the delta modulation technique, the digital encoded signal is derived

  analog input signal by comparison, at intervals

  the clock-synchronized periodicals of the value of the analog input signal during the previous time interval with respect to the value of the analog input signal of the interval

  present to determine whether the signal is increasing or decreasing

  nution, a bit "1" being generated if the comparison indi-

  An "O" bit is produced when the comparison indicates a decrease. When decoding the digital signal for each binary signal at "1", a predetermined amount is added to the last value of the analog output signal. , and when decoding the digital signal

  for each binary signal at the "O" level, a predetermined quantity

  mined is deducted from the last value of the output signal

  The predetermined quantity that is added or

  the previous value of the analog signal being fixed,

  this technique is referred to as fixed or non-adaptive delta modulation.

  tive. One advantage of the fixed delta modulation technique is that a low level (equal to several times the increment of step size) of the white noise (called "shaky" noise) can be added to the analog signal at the same time. encoding of

  this one to ensure that the noise floor is white.

  Otherwise, tonal noises (noise other than white noise)

  risk of being in the background, and a distortion of

  low calf can occur in the reconstructed analog output

of the decoder.

  The major difficulty of this type of delta modulation technique is the ndace of the appearance of errors during the decoding of the

  digital signal A type of error that occurs is due to the

  encoder ds with respect to the rate of change of the original analog signal, a phenomenon referred to as "slope overload" that occurs when the signal changes rapidly More precisely, if the decoding pence (i.e. to say the importance

  the amount that is added or subtracted from the

  previous decoder) chosen for the decoding does not correspond approximately to the slope of the initial input signal, there will be an appreciable error between the input analog signal

  introduced into the encoder and the analog output signal

  If the increment size (ie the decoding slope) is kept constant, the input can only be encoded accurately over a narrow range of amplitude changes because a change in the amplitude of the increment (ie the decoding slope) is maintained. important of the amplitude of the input signal during an interval

  clock synchronization (that is, a larger quantity

  than the amount of the increment) can not be reproduced with

  accuracy in the decoded output Faced with such an important change

  both of the input, the encoder will code a continuous stream of "1" bits or "O" bits to try to move up or down

  exit quickly enough to line up with the entrance.

  Another type of error that occurs with fixed delta modulation techniques is the "quantization" error that occurs when there is too little change in the

  analog input signal during the synchronization interval

  These errors appear when the

  step size of the reconstructed analog output signal de-

  continually pass the actual incremental value of the initial analog input signal during this time interval

  (when the actual change of the initial signal during the interval

  the time is less than the incremental amount added), producing a sawtooth signal composed of bits "1" and "a"

  in the digitally encoded signal.

  If you increase the step size, that is, the increment added to the decoded analog output signal, you can reduce the

  slope overload problem and thereby improve the adaptation

  tation at the speed of change, but at the same time increases the problem of optimization errors.

  step size, we reduce the problem of optimization errors.

  but increases the problem of slope overload and

  decreases the decoder's ability to adapt to the speed of change.

  ment. The operation of the system can be improved by reducing

  the duration of each discrete time interval, but this leads to

  do not increase the bandwidth and, therefore, the

cost of the system.

  To solve the problems of band overload and quantization errors, adaptive delta modulation systems, such as those described in US Pat. Nos. 4,190,801 and 4,254,502, have been developed. circuits making it possible to vary the increments added to the analog signal reconstructed or decoded so as to vary the slope and consequently to follow more closely the analog input signal.

  therefore a more extensive dynamic operating domain.

  These systems generally comprise means for generating

  signals, such as an integrator responding to a reference signal

  preferably, the reference signal is varied according to the amount of the incremental change of the initial analog signal during a certain time interval relative to the value of the

  signal of the previous interval, which allows the use of

  reference standard for modifying the magnitude of the increment that is added to the analog signal or that is subtracted from it when decoding the digitally encoded signal. US Pat. Nos. 4,194,801 and 4,254,502 each describe a system. adaptive which pi + mnet to vary the magnitude of the increment, that is to say the step garner, the encoder in proportion to the average of its derivative dc lu squared of the derivative) of the signal of entrance, this

  The average is ablie over many synchronization cycles.

  If adaptive signal salts make it possible to increase the domain dy-

  On the other hand, they bring disadvantages.

  The way to continually change the step sizes of the decoder output also results in continual changes in the quantization noise of the decoder output.

  vibrating sound to mimic this noise of quantification.

  cati on, you have to modify the vibrating sound at the same time as the

  change of step size to eliminate distortion

  For this reason, we do not generally use

  r: 1 l of vibrating noise in adaptive delta modulation systems

  As a result, the background noise may have a detrimental tone.

  to be unacceptably formed. In addition, when

  step quantization, the quantization error of the system changes with the signal level, which in turn produces a noise floor that moves

  a ', do, if this mobile placqqher is not far enough

  below the signal, it will not be properly masked, and we risk hearing a sound of "breathing" In addition, in typical adaptive systems, we can not change the size of not that d Jans a field between 500 and 1 , thereby limiting the dynamical domain of the system In addition, a step size

  minimal is imposed by the non-ideal behavior of a comparator

  which is used to compare the level of the analog input signal

  than the reference signal The non-ideal comparator is insensi-

  to differences in the signal levels falling below

  a minimum level that depends on the quality of the component.

  It is an object of the present invention to substantially reduce or eliminate the disadvantages of the prior art. Another object of the present invention is to provide an improved system for encodrr an analog signal in digital form and to decode the digitally encoded signal to accurately reconstruct the initial analog signal with a digital signal.

minimum deformation.

  Another object of the present invention is to provide an improved delta modulation system having the aforementioned advantages of adaptive and non-adaptive systems while substantially solving or reducing problems associated with disadvantages. Another object of the present invention is to provide a

  delta modulation system having a variable output slope

  using a fixed step size when decoding the

  digital encoding, while at the same time enabling us to use

  sound vibrating noise to mask the quantization noise.

  Another object of the present invention is to provide a

  delta modulation system suitable for transmission and recording.

  recording of audio signals and having a variable output slope

  using a fixed step size when decoding the

  digital encoded without moving the noise floor of

perceptible way to the ear.

  Another object of the present invention is to provide a

  delta modulation system with a functional domain

  dynamic to improve compared to adaptive systems

  and non-adaptive of the prior art.

  Another object of the present invention is to provide a delta modulation system which is practically insensitive to

  behavior of a non-ideal comparator.

  Another object of the present invention is to provide a

  delta dulator of the type in which the signal is adapted to a fixed step size according to analog techniques in order to

  enjoy the benefits of adaptive and non-adaptive systems.

  Another object of the present invention is to provide an inexpensive analog-to-digital converter using analog techniques. To achieve these and other objects, the present invention is directed to an improved signal encoding and decoding system. In one aspect, the present invention provides a system for (1) encoding an analog signal in the form of a signal. digitally encoded type comprising weighted binary signals each set during a discrete time interval and as a function of the difference between the signal value

  analog input during the interval and a reference signal

  established in accordance with a predetermined number of

  of the analog input signal for a predetermined number of

  corresponding interval or, alternatively, (2)

  encoding the digitally encoded signal to reconstruct the initial analog signal The system comprises means responsive to the digitally encoded signal for generating a control signal as a function of the digitally encoded signal.

  in addition to means sensitive to the control signal to make

  the gain printed on the analog signal according to the

control signal.

  In another aspect, the present invention provides a system for generating a digital encoded electrical output signal representative of, and in response to, an analog electrical input signal. The system includes output signal generating means digitally encoded so that the output signal comprises weighted binary signals, each for a discrete time interval and as a function of the difference between the value of the analog input signal during the interval and a reference signal as a function of a predetermined number of previous values of the analog input signal during a corresponding predetermined number of time intervals The system further comprises means responsive to a control signal for varying the gain of the signal printed on the input signal analogue and means of generating the

  control signal in response to the digitally encoded output signal.

  America. In another aspect, the present invention provides an improved system for producing a digitally encoded electrical output signal representative of, and in response to, an analog electrical input signal.

  means for producing a first analogue signal in

  the present value of the analog input signal, and signal generation means for producing a second

  signal based on a comparison between the first analogue signal

  logic and a third analog signal, the latter being

  the previous values of the analogue input signal

  a predetermined number of discrete time intervals pre-

  The system further comprises means responsive to the second signal for producing the digitally encoded signal. The latter comprises a weighted binary signal train. Each of the weighted binary signals is generated during a corresponding discrete time interval, the binary value of each of the signals. weighted binaries being a function of the first and third

  analog signals during the corresponding time interval.

  In another aspect, the present invention provides a system for producing an analog output signal by

  response to a digital encoded electrical input signal

  Analog output signal present The input signal

  digital-encoded electrical system includes binary signals

  each time during a discreet time interval and

  tion of the difference between the value of the analog output

  during a time interval and a reference signal according to a predetermined number of previous values of the analog output signal during a corresponding predetermined number of intervals. The system comprises means for

  generation of a first analog signal according to the

  digitally encoded signal during a preselected

  discrete time intervals, means responsive to a control signal for varying the gain of the printed signal

  on the first analog signal according to the control signal

  in order to obtain the analog output signal, and means responsive to the digitally encoded input signal to produce the

  control signal according to the digitally encoded signal.

  An embodiment of the present invention will now be described by way of example with reference to the accompanying drawings in which:

  Figure 1A is a schematic diagram of the mode of

  preferred embodiment of the signal encoding unit according to the present invention.

  a figure i B is a schematic diagram of the mode of

  the signal decoding unit according to the present invention;

  FIGS. 2A and 28 are circuits of the embodiment of

ir: Pref r of the encoding unit and

  l ,; Fig:, = es 3 'A and: 3 B are circuits of the mode of realization

  ioan óxeference of the decoding unit

  on the drawings, the same numbers designate the same

m ,, ts uu similar elements.

  Referring to FIG. 16, the encoding unit comprises an input horn -g O capable of receiving an input signal of an analogical nature which is used to amplify an audio or video signal. 10 is connected to the signal input terminal 12 of a gain module 14 This is a device for varying the signal gain printed on the analog signal signal. appearing at the input terminal 12 in the proportion of a control signal applied to an input terminal of the module to obtain at its roo-1 terminal; It is possible to use any of a signal multiplier of the type used to vary the gain of the signal, such as the amplifier controlled by a dynamically modified analog output signal. the tension achieved in the form of

  circuit n Ité: J Ir and marketed by dbx, inc, of Newton, Massa-

  chusetts (the present assignee), or that described in Emericoirn Patent No. 3,714,1162 issued to David E. qlackmer In general, such a voltage-controlled amplifier functions as a signal compressor to compress

  dynamically the analog signal according to the level of the

  command signal This type of compression technique

  and the complementary expansion technique are described in U.S. Patent No. 3,789,143 issued to David E. Blackmer. The analog nettle signal on the output terminal 18 is applied in a positive direction on the

  summation 20 The output of this last one is applied on the

  The comparator 22 compares the signal from the junction 20 with the system ground.

  22 delivers two types of signals * (a) a signal of polarity po-

  sitive when the signal applied to the comparator from the junction 20 is a positive signal and (b) a negative polarity signal (including zero volt signals) when the signal applied to the comparator from the junction 20 is

a negative signal.

  The output of the comparator 22 is preferably applied to the input of a circuit for periodically sampling the state of the output signal of the comparator 22, and producing a

  weighted binary signal indicative of this state for each

  time zone The sampling and signal generation circuit preferably consists of a D-type flip-flop 24,

  which is punctuated by a clock 26 According to the theories of exchange

  In a well known manner, the frequency of the clock signal must be at least twice that of the highest frequency of the expected frequency spectrum of the analog input signal applied to the input terminal. For example, if the analog input signal is an audio signal located in a frequency spectrum up to 20 000 Hz, the frequency of

  Rhythm provided by the clock 26 must be at least 40,000 Hz.

  Flip-flop 24 provides a weighted binary signal stream, each for a discrete time interval (i.e.

  clock interval established by the clock.

  weighted signal at a first binary value when the signal sent by the comparator 22 to the D-type flip-flop is a signal

  positive and a second binary value when the input of the

  cule is a null or negative signal It follows from the above that the digitally encoded output signal appearing on the

  output terminal of the encoder represents the input signal

  logic in digital form, each weighted binary signal con-

  holding information regarding the slope of the analog signal

  for the corresponding time interval.

  For reasons that will be better understood below, two feedback loops are provided by connecting the terminal of

  output 28 to a filter to obtain an analog signal representing

  past history of the slope of the analog input signal.

  This filter preferably comprises a signal integrator 30, the input terminal of which is connected to receive the digital signal delivered to the output terminal 28, and which is connected to the terminal 10 for a predetermined number of previous discrete time intervals. a "linear prediction filter" 32 connected to receive the output of the integrator 30 and having its output read in a negative direction at the junction 20 Generally, the integrator 30 performs the time integration of the output signals the digital output signal is of a binary value (for example, a high logic level to indicate a positive signal sent by the comparator 22 on the flip-flop 24) the digital signal appearing on the terminal 28, so that

  The output of the inverter is a signal that increases po-

  sitive and, when the digital output signal has the other binary value (for example, a logic low level to indicate a null signal to the negative sent by the comparator 22 on the flip-flop

  24) the solstice of the integrator is a decreasing signal of

  negative The linear prediction filter 32 provides a

  analog output which increases or decreases with the

  Increasing or decreasing targets at the output of the integrator The filter preferably comprises a capacitive device which functions as signal storage devices, as will be seen hereinafter, so that its analog output signal is representative of the values of the signal of the signal. analog input on terminal 10 for a predetermined number of previous time intervals. It should be noted that the loop constituted by the junction 20, the comparator 22, the flip-flop 24, the integrator 30 and the filter 32 functions as a fixed delta modulator because it does not allow

  not to vary the step size when encoding in me-

  for example, the derivative or square of the derivative of the original analog input signal The loop provides a signal of

  digitally encoded output comprising a binary signal stream

  Weighted rests Each of the weighted binary signals is generated during a predetermined discrete time interval determined by

  a clock 26 and is indicative of the increase or decrease

  the slope of the analog signal with respect to the values

  stored by the analog linear prediction filter.

  As the junction 20, the comparator 22, the

  24, the integrator 30 and the linear prediction 32 function-

  all of them as a fixed delta modulator, a source 36 of vibrating noise added in positive direction can be provided at the junction 20 for

  avoid any tonal modulation during decoding.

  To obtain the control signal applied to the control input terminal 16 of the module 14, there is provided a level detector 34 whose input is connected to receive the analog output of the integrator 30 and the output is connected to the terminal 16 of the module 14 The detector 34 may be a device of any type capable of producing an output signal according to

  the amplitude of its input signal The device is of pre-

  of a type for obtaining an output signal as a function of the value of the root of the square mean of its input signal and, for example, may be a detector of the root of the average of the squares of the type manufactured and marketed by dbx Inc. of Newton in Massachusetts and described in U.S. Patent No. 3,681,618 issued to David E Blackmer on August 1, 1972 Alternatively,

peak or average.

  The digitally encoded output signal appearing on the band 28 may be recorded, stored, transmitted or otherwise processed by known digital techniques in accordance with

  For example, when processing audio signals, the digitally encoded signals can be processed using a videoseope to record the signal on a video tape.

  For the decoding of the digitally encoded signal by the

  In FIG. 1A, the decoder shown in FIG. 1B is preferably used. The digitally encoded signal is applied to the input terminal 40 which, in turn, is connected to the filter constituted by FIG. integrator 30 A and filter dc) linear linear reduction 32 AM The integrator 30 A and the filter 32 A are identical to the integrator 30 and the filter 32 of the enec-de'r of Figure 1A The integrator 30 A converts the digital encoded signal applied to the input terminal 40 to an analog signal. The output of the integrator 30 A is connected to the input of the filter 32 A. The latter operates in the same manner as the filter. -A to sleck the past history of the samples of the analog inputs for the preselected intervals encoded in the digital input terminal The output of the 32 A filter is connected to the input terminal 12 A of the gain control module W 4 Who has san gold at its output terminal 18 A connect 2 n set terminal 42 of the decoder to obtain the reconstructed analog signal The output e of the level detector 34 A is mounted substantially responsive to the output of 13 'integrator 30 A and has its or e zeki at ia Command input terminal 16 A of module 14 A. The noedc :; The detector 311 A of the decoder is respectively identical to one of the modulators 14 and to the detector 34 of the encoder.

  difference is that the output of the detector 34 A is inverted and the

  1 is adapted to ensure the expansion of the complimentary signal the compression of the signal provided by the module 14 di * 'e: nacdeur of Figure' A 2 in accordance with the teaching of 3 C br eve-ve cien Y 789 143 He was noted when it will be

  clearer in isan a description of FIGS. 2A, 2B, 3A and 3B,

  that all comnosar Ls of the decoder are included in the encoder of seret that i only one set with eoprouple switching circuits can be used to perform the encoding and decoding -: implement by eomremutant this only set between two modes of operation during the decoding of the digitally encoded signal using the decoder of FIG. 1B, the latter signal is applied to the input band 40 The digital signal is converted into a signal

  analogy by integrator 40, the analog signal increases

  or decreasing according to the binary value of each

  weighted binary signal applied to terminal 40 The analog output

  Integrator 30 A is applied to the prediction filter.

  The 32A filter stores the values of the analog output of the integrator 30A to represent the past history of the analog output signal.

  of the integrator, so that its value is the corresponding value.

  the signal appearing on the output terminal 18 of the module 14 after the compression of the signal during the encoding during

  the particular time interval Because the output of the thread

  32A represents the output in the form of a compressed signal from the encoder module 14, the signal must be expanded by

  Complementary way Module 14 A ensures the complete expansion

  the output on terminal 42 is a reconstructed version of the original analog signal present on the

input terminal 10 of the encoder.

  In FIGS. 2A and 2B, the details of the circuits of the preferred embodiment of the encoder are shown. As can be seen,

  the input terminal 100 of the decoder receives the input signal

* initial logic The input terminal 100 is connected by the capacitor

  102 to a resistor 104 which, in turn, is connected to the input of a voltage controlled amplifier (VCA) 106 of a type described in US Patent No. 3,714,462 issued to US Pat.

  name of David E Blackmer on January 30, 1973, or one of the amplifi-

  Controllers controlled by the voltage commercialized by the company known as dbx Inc., Newton, Massachusetts The output of the VCA 106 is connected to a current-voltage converter comprising the amplifier

  The amplifier 108 has its non-inverting input

  connected to the system ground and its inverting input

  mounted to receive the output of the VCA 106 The output of the amplifier

  indicator 108 is connected to its inverting input by the circuit

  consisting of resistor 110 and capacitor 112 in parallel

  The output of the amplifier 108 is also connected to the input of the delta-114 modulator. The modulator 114 comprises a low-pass filter 116, a comparator 118, a D-type flip-flop, a level-shifter 122, integrator 124 and a linear prediction filter 126. Specifically, the filter 116 comprises a resistor 130, one end of which is connected to the output of the amplifier 108 while the other end is connected by the capacitor 132 to the system ground and, by the resistor 134, at the point of comparison of the summing junction 136, the latter also being connected to the input of the comparator 118 The comparator 118 may be any one of several such devices which are well known in the art and consists of

  preference of a type called differential pair gain stage-

  the. As can be seen in the figure, the output resistor 134 of the filter 116 is connected by the comparison point 136 to the base of the NPN transistor 140. The emitter of the transistor 140 is

  connected to the emitter of a matched NPN transistor 142 to realize

  The emitters of the transistors 140 and 142 are connected together by the resistor 144 to a capacitor 146 which, in turn, is connected to the ground of the transistor.

  The resistance 144 is also connected by a resistance

  this 148 and by a capacitor 150 has the system mass La

  connection between the resistor 148 and the capacitor 150 is po-

  The base of the transistor 142 of the differential pair is grounded, while the connectors of the transistors 140 and 142 are connected to the opposite side of the capacitor 152. The collector of the transistor 140 is connected to the opposite side of the capacitor 152.

  also connected by the capacitor 154 h each of the capacitors

  156 and 158 Each of the capacitors 156 and 158 are

  linked, in turn, to the mass of the system.

  sistor 140 is also connected by a resistor 160 to a source

  This is a positive DC voltage. The collector of the transistor 142 is connected by a resistor 162 to a DC voltage source.

  positive The collectors of transistors 140 and 142 are also

  respectively connected to the inverting and non-inverting

  version of an operational amplifier 164, which provides the output of the comparator 118 The output of the comparator is connected

  to a source of positive DC voltage applied to a resistor

  166 which in turn is connected to the input D of the D-type flip-flop 120. The flip-flop 120 is clocked by the clock 123 which provides a clock signal at a frequency which is at least twice the highest expected frequency of the input signal

  analogue applied to the input terminal 100 The output terminal

  Q tie of the flip-flop provides the digital output of the encoder to

  the output terminal 121 The output Q of the flip-flop 120 is also

  connected by an inverter of the digital signal 168 to the

  tif level shift 122 Specifically, the output of

  the inverter 168 is connected to a positive DC voltage source

  The output of the inverter 168 is applied by the line 172 to the resistor 174 which, in turn, is connected by a resistor 176 to a voltage source.

  continuous negative as well as the entry of an integrator 124

  The integrator 124 is connected to the inverting input of an operational amplifier 178 which has its non-inverting input.

  grounding the system The output of the amplifier

  The output of the amplifier 178 is further connected to the input of the linear prediction filter 126 as well as to the feedback capacitor 180 and the feedback capacitor 182. at the input of a low-pass filter 210 described with reference to FIG.

2 B below.

  More particularly, the output of amplifier 178 is

  connected by the resistor 180 of the filter 126 to the output of the

  The filter output is connected by the capacitor 182 to the

  resistance 184 which, in turn, is grounded to the system.

  The output of the filter 126 is connected by the resistor 186 to the comparison point 136. The filter 136 therefore constitutes a

  RC network comprising resistors 180 and 184 and the capacitor

  182 designed to load and unload at a speed

  about 400 to 600 times slower than sample speed-

  123, although these limits may vary to a certain extent. By way of nonlimiting example, if the analog input signal is an audio signal between 20 Hz and 20 k Hz and the frequency of the clock signal provided by the clock 123 is about 700 kHz, the resistors and 184 have values of 200 and 33 ohms, respectively, and

  the capacitor 182 has a value of 0.068 microfarads.

  turn ensure better tracking of the input analog signal

  digital ciphering, the output of the modula-

  11 q h the output terminal 121 of the encoder is applied to

  the transient acceleration input 200 More precise

  In this case, the output port 121 is connected by the resistor 202 to a positive DC voltage source and directly to the input of a digital edge detector 204, the latter providing a pulse for each transition going into the positive sense and

  for each transition in the negative direction that appears

  on the exit sign 121 The exit of the front detector

  2.04 was applied in turn to the entry of a multi-stage vibrator.

  nstabl 206 turns its output Q connected to the base of the transceiver OPN 208 z The latter has its collector connected directly to a source 6: positive DC voltage The resistor 210 serves

  of the output of the single-stage multivibrator

  The stability of the transmitter of transistor 208 is

  nd by a network fill: t at the exit of the pre-emptive network.

  232, which will be described hereinafter with reference to FIG. As mentioned above, the output of the opto-arterial amplifier J i, 8 of the uninterrupted 12/4 is connected to the input of the pssse fi rst. - ;: a; third-order 2 -'10, shown in Figure 28 This filter comprises an input resistance 212 which is connected

  (a) by the capacitor 214 to the system's mass and (b) directly

  2 Resistance 216 is connected by the

  capacitor 11.8 to resistor 220 which, in turn, is connected

  This resistor 216 is also connected to the resistor 222, which in turn is connected; on the one hand, by the capacitor 224 to the system ground and, on the other hand, directly to the resistor 226 This latter resistor is connected to the base of the NPN transistor 228 whose collector is connected to a positive DC voltage source and whose emitter is connected by resistor 220 to a source of negative DC voltage The output of filter 210, output

  the transmitter of transistor 228, is connected to a capacitor

  The latter is connected, in turn, to the input of the pre-emphasis network 232 The pre-emphasis network 232 pre-sets the high frequencies in the detection path so that the amount of gain printed on the analog signal by the amplifier VCA 106 is generally lower for

  high frequencies only for low frequencies The pre-emphasis

  For example, see U.S. Patent Nos. 4,101,849 and 4,136,314 issued to Blackmer et al. The input of the network 232 is connected by a resistor 234 to the device. its output and by a capacitor 236 to a resistor 238 which, in turn, is connected to the output of the network The network is also connected by a resistor 240 to the resistor 242 which, in turn, is connected to the output 209 of the The resistor 240 is further connected by the capacitor 244 to the system ground. The output of the network 232 is connected to

  the input of a level detector 250.

  As described with reference to FIG. 1A, the detector 250 is preferably of the type capable of outputting a signal which is a function of the value of the root of the average of the squares of its input signal. such detectors are well known in the art and, for example, may be of the type described in US Patent No. 3,681,618 issued to David E Blackmer or the type marketed by dbx, Inc. Newton, Massachusetts Si a detector of the root of the average of the squares of the type marketed by the company dbx, Inc., in the form of a chip, the input is

  applied to pin 1 of the chip while the pin

  7 gives the output Preferably, pin 6 is connected to

  a double circuit of time constant 251 to ensure a

  Loose or fast discharge when discharging at the chip output for large signal changes at the input and a low ripple, or slow-change signal at the output for steady-state input signals Such circuits are well known in the art and are not part of the present invention. As can be seen, pin 6 is connected by resistor 252 to a negative DC voltage source.

  and by the capacitor 254 at the inverting input of an amplifier

  The latter has its non-inverting input connected to the system ground and its output connected to its input

  reversal by parallel mounting of a feedback resistor.

  258 and a feedback capacitor 260 The output of

  the amplifier 256 is further connected to (1) the ring of the diode

  of 262 and the cathode of the diode 264, which, in turn, have their cathode and respective anode connected to the inverting input of the amplifier and (2) by a capacitor 266 at the junction of

  pin 6 and resistor 252.

  The output of the detector 250 is connected to the amplifier

  The non-inverting input of the amplifier 268 is connected by a resistor 270 to the ground and by a resistor 272 to the arm of a potentiometer 274. The latter has opposite ends respectively connected to positive DC voltage sources or negative The output of the amplifier 268 is further connected, on the one hand, by a feedback resistor 276 to

  its non-inversion entry and, on the other hand, directly to

  VCA amplifier control signal 106 shown in FIG. 2A. Finally, if the VCA amplifier 106 does not produce sufficient noise, a noise generator 280 connected by a resistor 282 to the comparison 136, to produce

wave noise.

  Figures 3A and 3B show the preferred decoder for

  to decode the digital encoded output signal established by the

  encoder shown in Figures 2A and 2B and appearing on the output terminal 121 To decode the digital signal, it is applied to the input terminal 300 shown in Figure

  3 At input 300 is connected to the nib shifter

  caliber 122 A by a connection between the input terminal 300 and the input

  of the digital signal inverter 168 A The output of this invert-

  168A is connected by a resistor 170A to a positive DC voltage source and a resistor 174A to the indicator 124A. The input of the integrator 124A is connected to the inverting input the amplifier 178 A has its non-inversion input connected to the system ground and its output by a feedback resistor 181 and a capacitor 182 A The inverting input of the amplifier 178 A is connected by a resistor 176A to a negative DC voltage source The output of the amplifier 178A is connected to the linear prediction filter 126A The latter has its input connected by a resistor 180A to the capacitor 182A which, in turn, is connected by a resistance 184 A to the system ground The resistor 180 A is also connected to the output of the filter 126 which, in turn, is connected to a capacitor 302 The latter is connected by a resistor 304 to

  a capacitor 306 which, in turn, is connected to the bulk of the system.

  Resistance 304 is applied, as shown in Figure 38? to the resistor 308, the latter being connected to the input of the amplifier VCA 106 A The latter has its output connected b a

  voltage-current converter comprising the operational amplifier

  The amplifier 108 A has its non-inverting input connected to the system ground while its output is connected by the parallel mounting of the feedback resistor 110A and the

  capacitor 112 A The output of amplifier 108 A is also

  connected by a resistor 307 to establish the terminal of

  output of the decoder to provide the analog output

built.

  The input terminal 300 is furthermore connected by a transient acceleration circuit 202 A complementary to that used for the encoding method. More precisely, the input terminal 300 is connected by a resistor 202A to a source. positive current voltage, as well as the input of the transient acceleration circuit 202 A The input of the circuit 202 A is connected to the input of the digital edge detector 204 A which, in turn, has its output connected to the monostable multivibrator 206 A. The latter has its Q output connected to the base of the PNP transistor 208 A The latter has its collector connected to a positive DC voltage source The resistor 210 A operates as a "rising" resistor of the output of the monostable multivibrator 206 A The

  output of circuit 202 A is available on the transmitter of the transis-

  tor 2 USA and is applied at point 209 A. As described above with reference to FIG. 1B, the control signal applied to the gain control module is sensitive to the output of the indicator By therefore 9 as

  As shown in FIG. 3A, the output of integrator 124A is

  connected by a resistor 212 A to a capacitor 214A which, at its

  turn, is connected to the system's lsasse The junction of the resistor

  -15 tanee 2 t 2 A and capacitor 214 A is connected by a resistor

  216 A to a capacitor 218 A and a resistor 222 Ao The capacitor

  21A is connected by a 220A resistor to a source of

  Negative DC voltage Resistor 222 A is in turn

  It is connected by a capacitor 224 to the earth of the system. The junction of the resistor 222 of the capacitor 224 A is connected to a capacitor 224.

  resistance 2326 f which, in turn, is connected to the basis of

  The transistor 228 A has its collector connected to a positive current transistor and its emitter connected to the transistor.

  jonei on capacitor 218 A and resistor 220 A the transmitter

  Lransstor 228 A is also connected to the capacitor

  230 A This denier is connected, in turn, to the pre-accentuation network.

  327 A: The latter S its input connected by a resistor 234 A

  the capacity of the network and a capacitor 236 A with a resistor

  -2 e 23 e A, the latter being also connected to the output of the network 232 AL output of the network 232 A is connected to a resistor 240 A which, in turn, is connected by a resistor 242 A to 12 D 9 A of the output of the transient acceleration circuit 202 A and,

  Fpal a conds: isate Jr 244 A, to the mass of the system The output of the re-

  bucket P: ZA st Eement connected to the input of the level detector 250 A, Figure 2; The double circuit of time constant 151 A is rn ii at the break if the 250 Ao breaker The circuit 251 A is

  identical to the circuit 251 in FIG. 2 B pin 6 is

  connected by a capacitor 254 A to the inverting input of the amplifier

  The latter has its non-inverting input connected to the system ground and its output connected to the cathode of a diode 264 A and to the anode of a diode 262 A. The cathode of the diode 262 A and the diode 264 A are both connected to the inverting input of the amplifier 256 A The output of

  the amplifier 256 A is also connected to its invert input

  256 A by a parallel mounting of a resistor 258 A and a feedback capacitor 260A The output of the operational amplifier 256 A is further connected by a capacitor 266 A to the pin six of the detector 250 A and to resistance 252 A which, at

  in turn, is connected to a source of negative DC voltage.

  The output of the level detector 250 A is connected, as it is

  see Figure 3B at the non-inverting input of an amplifier.

  268 A The latter has its reversal input connected by a

  270 A to the system ground and a 272 A resistor to the

  274 A potentiometer arm This is connected

  The output of the amplifier 268 A is connected, on the one hand, by a feedback resistor 276 A to its inverting input and, on the other hand, directly to the input terminal of the control signal of the amplifier VCA 106 A. In operation, an analog information signal (in the form of a voltage signal) is applied to the input terminal of the encoder 100 of Figure 2A The input voltage signal is converted into a current by the capacitor 102 and the

  resistance 104 before being applied to the input of the amplifier.

  VCA 106 This prints a signal gain on the signal according to the control signal produced by the level detector 250 and available at the output of the amplifier 268. As already mentioned, the output of the The VCA amplifier 106 is a dynamically compressed analog signal. This signal is converted into an analog voltage signal which, in turn, is applied to the input of the low-pass filter 116 of the modulator 114. The filter 116 eliminates any unwanted high frequency that may be present. on the signal The analog voltage output of the filter 116 is applied to the comparison point 136 where it is compared

  (that is, added algebraically) to the analog voltage output

  As will be seen below, the filter 126 provides an analog voltage as a function of the past history of the values of the analog voltage output of the low-pass filter 116 for a predetermined number of times. previous time intervals previous

  immediately the present interval determined by the clock 123.

  The analog voltage output of the linear prediction filter is also inverted so that, if the voltages are equal, the comparison point 136 will be at the ground potential of the system. During the time interval necessary to perform the comparison, if the amplitude of the output voltage of the filter 116 is greater than that of the filter 126, the voltage at the point of

  comparison 136 will be positive Comparator 118 will always try

  days to bring his entry to the point of comparison 136 to the

  the mass of the system, as is well known in the

  This positive voltage input at the point of comparison

  its consequence is that the output of the comparator 118

  negative comes D input 120 of the flip-flop being negative during the instant o the timing pulse is received by the flip-flop from the clock 123, the Q output of the flip-flop will be a low level weighted binary signal indicative of an increasing signal for this time interval This signal is applied to the output terminal 121 of the encoder as part of the

  digitally encoded signal The binary signal is also in-

  poured by the inverter 122 so that the output of the inverter is a high level weighted binary signal This high level digital signal, in the form of a positive voltage pulse, has its voltage level increased by the device. level shift 122 before being applied to the integrator 124 The integration of the pulse is performed to convert it to an analog voltage during the determined time interval

  by the clock 123 Since each digital pulse output

  If the level shift device contains substantially the same amount of signal energy, the incremental output of the integrator for each pulse (i.e. step size) will be the same. This incremental output, positive voltage ,

  is applied to the input of the analog linear prediction filter

  it is stored (that is, it loads the capacitor 182 to a higher value). On the other hand, if,

  during the period of time necessary to perform the comparison

  at point of comparison 136, the output voltage of the

  116 has a smaller amplitude than the output of the

  filter 126, the voltage at the point of comparison 136 will be negative.

  The comparator 118 will again attempt to bring its input to the comparison point 136 to the ground potential of the system so that the negative voltage input applied to the comparison point 136 causes the output of the comparator 118 to become positive. input D of the flip-flop 120 being positive

  during the moment when the rhythm pulse is received by the

  from clock 123, the Q output of the flip-flop

  will be a high level weighted binary signal indicative of a

  This signal is applied to the output terminal 121 of the encoder as part of the

  digitally encoded signal The binary signal is also in-

  poured by the inverter 122 so that the output of the inverter will be a low level weighted binary signal This low level digital signal, in the form of a negative voltage pulse, has its voltage level increased (made more negative in the same proportions as for a positive voltage pulse so as to contain the same amount of signal energy) by the device

  level 122 before being applied to the integration

  The integration of the impulse is carried out for the conversion

  analog voltage shooting during the determined time interval

  by the clock 123 Since each digital pulse output

  of the level shifter contains substantially the same amount of signal energy, the incremental output of the integrator for each pulse (i.e., the step size) will be the same. This incremental output, voltage negative

  is applied to the input of the analog linear prediction filter

  where it is stored (that is, it reduces the

  charge, and therefore the voltage, on the capacitor 182).

  To produce the control signal, the output of the integra-

  The detector 124 is applied after passing through a low-pass filter 210 to eliminate unwanted low frequencies on the pre-emphasis network 232. The detector 250 outputs a continuous sigral based on the value of the root of the average of the signals. squares of the input from the network 232 The output of the detector 250 es; This amplifier has the function of compressing the analog signal so that the compressed signal is, in the dynamic sense, more closely adapted to the VCA amplifier.

  fixed modulator 114 in order to obtain a better follow-up and a lower

  dre possibility of slope overload However, for signals with very fast operation, signals that the technique of

  compression 3 e not allow to accurately track, the output naked

  merique of the flip-flop 20 is applied to the acceleration circuit

transitional 280.

  In: ar-iculieró the weighted binary pulse train is

  This sensor detects a modification

  The output of the value, i.e., a high-to-low transition or up-down, of the digital output of the flip-flop 120 and provides a pulse in response to each transition.

  3th call at the entrance of a monostable multivibrator

  bie 20 i 6 cuhr each transi tion up down and down up, the

  multi-reaper monostbe will be amo rce and lta output Q of the multivi-

  At a low level, when there is a series of im-

  In the case of low or high level pulses (for example, about 20, although this number may be changed), the analog input signal increases or decreases at a rate of change that is too fast for allow the modulator to reactivate the monostable multivibrator to be de-energized, to pass Q output to level 0 to unblock transistor 20 where it becomes conductive to establish a current at point 209 (signal adds to the signal at the output of the pre-emphasis network 232 before being applied to the input of the detector 250. This results in an increase of the input signal applied to the input of the detector 250 and, consequently, of the output of the detector. control signal applied to the VCA amplifier 106 so

  to provide greater signal compression.

  When decoding the digitally encoded signal by the encoder of FIGS. 2A and 2B, the signal is applied to the input 300 of the

  decoder shown in FIGS. 3A and 3B. Each signal

  The weighted inverse is inverted by the inverter 168A and its amplitude is changed by the level-shifter 122A. Each signal is then applied to the integrator 124A, which functions in the same manner as the encoder integrator 124. When the binary signal is at level 0, it is in the form of positive voltage pulse The application of this voltage pulse

  integrator 124 leads to the integration of the impulse

  to be converted into analog voltage during the time interval (determined by the pulse repetition frequency of the digital input signal) Since each digital pulse contains substantially the same amount of signal energy, the incremental output of the integrator for

  each pulse (that is, the step size) will be the same.

  This incremental output, positive voltage, is applied to the input of the analog linear prediction filter 126 A o it

  stored (that is, it charges the capacitor 182 A

than at a higher value).

  On the other hand, if the binary signal applied to terminal 300 is at level 0, it is inverted and its amplitude is modified by the

  level-shifting device 122 A The inverted binary signal

  The low level signal is applied to the input of the integrator 124 A. This low level signal is in the form of a voltage pulse.

  negative and its integration is carried out to convert it into

  analog output during the time interval determined by the repetition frequency of the input signal pulses Each digital pulse output of the

  level containing substantially the same amount of energy of

  general, the incremental output of the integrator for each pulse

  sion (that is, the step size) will be the same This output

2535 130

  incremental, negative voltage, is applied to the input of the

  analog linear prediction 126 A where it is stored

  (that is, it reduces the load, and therefore the

  on the capacitor 182 A) The output is transmitted to the VCA amplifier 106 A gain is impressed on the signal to provide signal expansion as a function of the control signal from the level detector 250A. signal that is applied is the complement of the compression of

  signal established during the encoding process so that the signal

  at the output terminal 308 of the decoder is reproduced

  dynamically in its original form.

  To establish the control signal, the output of the integra-

  124A is filtered by the filter 210A before being applied to the pre-emphasis network 232A and then to the 250A detector. The output of the detector 250A, continuous signal having a value

  function of the root of the mean of the squares of the entrance of the de-

  The output of this amplifier supplies the control signal to the VCA amplifier 106 A. Finally, to ensure a correct amount of expansion when

  decoding of the digitally encoded signal, the digital input signal

  Terminal 300 A is applied to the edge detector 64 A before being applied to the one-shot multivibrator 106. This operates identically so that when a series of consecutive low or high signals appear on

  300, no signal is applied to the input of the multivariate

  This results in the output Q going to the level O and the transistor 208 A becoming conductive to add a signal to the input of the detector 250 A. It should be noted that all the components of the decoder are identical to the corresponding components. the encoder to ensure a precise reconstruction of the analog signal For this reason, although they are not shown, the two élémnenti can be made as a single unit, a switching system being provided for switch from one mode to another In addition, equivalent components known in the

  technical can be substituted for those described and shown.

  For example, other types of

  gain control, level detectors and predictive filters.

linear

  The system described has several advantages The advantages of a fixed delta modulator are obtained by using a modula-

  fixed delta 114 (and 114 A) for the encoding process (decoding).

  ge) and an adaptive delta modulator by varying the analog output of the decoder within each step size by implementing compression-expansion techniques Therefore, the system has a variable slope output using a step size fixed for signal decoding

  digitally coded, while being adapted at the same time to

  oscillatory noise to mask the noise of

  The system has a variable slope output using

  a fixed step size so that, when using the system for processing the audio signals, the digital encoded signal can be decoded without audibly

  noise floor Using compression techniques-

  signal expansion, the dynamic domain of the system increases significantly (120 d B or 1,000,000: 1) compared to

  that of the adaptive systems of the prior art (a maximum of

  30,000: 1) The system is virtually insensitive to

  port of a non-ideal comparator The signal is varied in steps

  analog technology in order to take advantage of the advantages

  of non-adaptive and adaptive systems in order to obtain a

  relatively inexpensive analog-to-digital converter.

  It should be noted that although the system represented by

  ge of an analog signal and decoding of a digital signal

  a single-band system, that is, all frequencies

  the analog input signal are processed in the same channel, multiple bands or channels can be used for encoding and decoding, the analog input signal being in this case filtered by bandwidth filters which divide the entire frequency spectrum of the analog input signal in lower frequency bands, encoded separately, subsequently decoded and put in combination to produce the reconstructed analog signal. It goes without saying that modifications can be made to the apparatus described and shown, without departing from the scope

of the invention.

Claims (19)

  System for generating a digitally encoded electrical output signal representative of, and in response to, a signal   analog electrical input, characterized in that take:   means (14) for providing a first analog signal   according to the present value of the analog input signal   cal; signal generating means (22) for generating a second signal as a function of a comparison between the first analog signal and a third analog signal, said third analog signal being a function of the previous values of said   analog input signal for a predetermined number of   previous discrete time periods, means (24) responsive to the second signal for generating said digitally encoded signal, said digital encoded signal comprising a weighted bit signal stream, each of the weighted bit signals being generated during a corresponding discrete time interval , the binary value of each of   weighted binary signals being a function of said first and third   sth analog signals during said discrete time interval. System according to claim 1, characterized in that the signal generating means (22) comprises means for generating a fourth signal as a function of the average of said weighted binary signals, and storage means (32) for storing said fourth signal during said number   predetermined period of previous discrete time intervals and for   the third analogue signal according to the fourth stored.   3 System according to claim 1, characterized in that the means (14) for providing the first analog signal comprises means (30) whose role is to vary the speed of change of the first analog signal according to   of a control signal so as to impose a limit on the speed of   change of said first analog signal.   4 System according to claim 3, characterized in that   means (14) for varying the gain of the combined signal   take an analog signal compressor.   System according to claim 4, characterized in that the analog signal compressor (14) comprises an amplifier (106) for varying the printed gain to said analog input signal as a function of said control signal and means (250) ) for generating the control signal according to said digital coded signal.   System according to claim 4, characterized in that the analog signal compressor comprises an amplifier (106) for varying the printed gains to said analog input signal as a function of said control signal and means (250) for generating the control signal depending   the amplitude of the analog input signal.   System according to claim 6, characterized in that   means (250) for generating the control signal   denote said control signal according to the value of the   root of the average squares of the analog input signal.   System according to claim 6, characterized in that it further comprises means for producing a fifth signal when a predetermined number of consecutive weighted binary signals have the same preselected bit value and said means for providing said command signal   according to said analog input signal and the fifth   gnal. System according to Claim 2, characterized in that the storage means (32) comprise capacitive means responsive to said fourth signal.   The system of claim 2, characterized in that the means for providing said fourth signal comprises signal integrating means (30) for performing the integration of the weighted binary signals to obtain said fourth signal.   11 System according to claim 10, characterized in that the storage means (32) comprise capacitive means responsive to said fourth signal.   System according to claim 1, characterized in that the signal generating means comprise means (136)   intended to establish algebraically the sum of the first and third   signals and producing an added signal in response thereto, and means (118) for comparing the added signal to the system ground and producing the second signal in accordance therewith. answer to this comparison.   13 System according to claim 12, characterized in that the second signal is of a polarity when the added signal is of a positive polarity and an opposite polarity when the   added signal is of negative polarity.   System according to claim 13, characterized in that the binary value of each of the weighted binary signals is   depending on the polarity of the signal added during the said inter- corresponding time range.   A system for generating a digital coded electrical output signal representative of, and in response to, an analog electrical input signal, characterized in that it comprises in combination: means (22) for providing said signal of digitally coded output comprising weighted binary signals, each for a discrete time interval and as a function of   the difference between the value of the analogue input signal   in said interval and a reference signal as a function of a predetermined number of previous values of said analog input signal for a corresponding predetermined number of said intervals; means (106) responsive to a control signal for   varying the printed signal gain to said analog input signal   logic; and means (250) for providing the control signal in   response to said digitally encoded output signal.   16 System for producing an analog output signal   logic in response to an electrical input signal coded in numerical   representative of said analog output signal, said   digital encoded electrical input signal including   weighted bits, each for a discrete time interval and as a function of the difference between the value of said analog output signal during said time interval and a reference signal as a function of a predetermined number of previous values of said analog output signal during a corresponding predetermined number of intervals, characterized in that it comprises:   means (30 A) for providing a first analog signal   in which the value of said digitally encoded signal is suspended for a number of seconds from said discrete time intervals of means (32A) responsive to a control signal for   vary the signal -ain of printed signal to said first signal   forcing said command signal to obtain said analogue output signal; and alo 7 un (34 A) sensibsles to the digitally encoded signal for   produce the control signal as a function of the signal coded in nu-   A system according to claim 16, characterized in that the means (30A) for producing the first analog signal comprises: means (178A) for providing a second signal as a function of the average of the signals weighted bits, and storage means (126A) for storing said second signal during said predetermined number of discrete time intervals   preceding and to provide said first analog signal in function tion of the second sinnal-stored.   1, Scote one-on claim 16, characterized in that   the Isen 3 14 A) t d 'dinees to vary the printed signal gain   analog signal include means for   9 born to make vielesse change of said first analog signal in fanction dudi L command signal to impose   a limit to the rate of change to said analog output signal   logic. 19 System according to claim 187 characterized in that the means (14 A) for varying the signal gain   include means for expanding the analog signal.   System according to claim 19, characterized in that the digital coded electrical input signal is a function of a variable signal gain printed on said analog output signal   in the sense of compression, and in that said means of ex-   analog signal pansion comprise means for varying the signal gain in a complementary manner by   in relation to the function of said variable gain.   System according to claim 19, characterized in that   the means for expanding the analog signal comprise an amplifier   indicator (118 A) for varying the printed gain at the first analog signal as a function of said control signal and means for providing said control signal as a function of the digitally encoded signal.   System according to Claim 19, characterized in that the means for generating the first analog signal comprise means for generating a second signal as a function of the average of the weighted binary signals and in that the means for expanding the analog signal comprise a amplifier (178 A) for varying the printed signal gain of said first analog signal as a function of said control signal and means for providing the control signal according to said signal.   System according to claim 22, characterized in that   means (250 A) for providing the control signal   this control signal according to the value of the   root of the average squares of the second signal.   24 System according to claim 22, characterized in that   it also includes means to provide a third   sth signal when a predetermined number of consecutive weighted binary signals have the same preselected bit value and in that the means for providing the control signal provide the control signal as a function of said second signal and said third signal.   System according to claim 17, characterized in that   the storage means comprise capacitive capacitive means to the second signal.   System according to Claim 17, characterized in that the means for providing the second signal comprise   signal integrating means (124 A) for performing the in-   tegration of the weighted binary signals to obtain said second signal. System according to claim 26, characterized in that   the storage means comprise capacitive capacitive means   sound to the second analog signal.   28 System for (1) encoding an analog signal as a digitally encoded signal of the type comprising   weighted binary signals, each of a time interval dis-   cret and depending on the difference between the signal value   analog input during said interval and a signal of   depending on a pre-determined number of prior values   of said analog input signal for a predetermined number of   corresponding interval, or (2) to decode the said signal   digitally coded so as to allow the reconstruction of the   analogue signal, characterized in that it comprises: means (34A) responsive to the digitally encoded signal for providing a control signal as a function of said digitally encoded signal g and means (14A) responsive to the control signal for make   variable Thr the gain printed on the analog signal by flipping said order form.