FR2534751A1 - RESTORATION CIRCUIT AT POWER ON FOR AN ELECTRICAL CONTROL SYSTEM - Google Patents

Abstract

THE INVENTION CONCERNS LOGIC CIRCUITS. A RESTORATION CIRCUIT ON SWITCHING ON 17 IS INCORPORATED IN AN INTEGRATED CIRCUIT 11 WHICH ALSO INCLUDES A CIRCUIT 16 INCLUDING AT LEAST ONE MEMORY ELEMENT WHICH MUST BE POSITIONED IN A DETERMINED STATE ON SWITCHING ON. THE RESTORATION CIRCUIT INCLUDES IN PARTICULAR A SERIES COMBINATION OF TWO FIELD-EFFECT TRANSISTORS T1, T2 WHICH DIVIDES THE APPLIED SUPPLY VOLTAGE VDD AND APPLIES THE DIVIDED VOLTAGE TO A HYSTERESIS S1 DOOR WHICH HAS TWO THRESHOLDS. APPLICATION TO ELECTRONIC MOTOR CONTROL.

Description

The invention relates to electrical control systems and carries

  more particularly on electrical control systems in which control is exercised by logical elements containing a memory, which require restoration (and maintenance) to an initial state at the time of power-up or when the voltage is interrupted The invention further relates to an electrical control system in which

  the control logic is incorporated in an integrated circuit.

  will. The invention addresses the problem that appears in

  an electronic control system which contains

  memories that may take random states.

  at the moment of power-up, and to produce an unwanted control command The invention relates to a means for

  able to define the initial state of such memory elements.

  when the power is turned on or if there is a

  This function is what we call the function of restoration at the time of the

voltage (RMST).

  In a prior-to-power-on restoration circuit of the so-called dynamic type, a voltage division between a resistor and a capacitor is detected to determine the fact that the integrated circuit has been energized. connected to the ground and the power resistance (Vdd), the

  connection between the resistor and the capacitor would be.

  nominal to ground and rise to the supply voltage (Vdd) at a certain slow speed The delay between the initial "O" state and the final "1" state would purposely provide an initialization period of sufficient time to restore all memory elements to an initial state

known and appropriate.

  In the known circuit, the power-up restoration may not work when the circuit is energized, if the positive supply voltage (Vdd) increases in a more progressive manner than the voltage on the capacitor in the circuit. In this case, the input signal of a gate detecting this voltage may be equal to Vdd, without significant reduction, and the input signal of the gate goes high (i.e. say "1")

  too early, which has the effect of blocking the door from

  when it becomes valid, and before it can protect the circuits In the case where the positive supply voltage (Vdd), when the

  circuit, increases more rapidly than the voltage on the con-

  in the RMST circuit, the RMST operates at power-up, as long as this condition is met, but if the supply voltage suddenly disappears for an interval too long

  in short to allow the discharge of the capacitor in the cir-

  RMST cooks, the latter ignores the transient state and allows it to disturb the memory In summary, a dynamic type RMST circuit, which is based on the detection of the voltage Vdd by a voltage division between a resistive element and a resistor. reactive element (capacitive in this case), does not offer total security under the most unfavorable conditions The technique of the invention therefore uses a so-called "static" RMST circuit, in which the detection of the voltage Vdd is accomplished by conductive, nonreactive, -independent elements of the speed of

variation of the voltage.

  It is desirable that a RMST circuit be

  with the manufacturing techniques of integrated circuits

  which are widely used in

  In this application, it is desirable that the cir-

  cooked RMST does not use non-integrable components and requires a minimum of pins, or preferably none,

  to connect the integrated circuit to the rest of the communication system

mande.

  An object of the invention is therefore to provide a

  Advanced Power-On Restoration Cook (RMST)

  for use in an electronic control system.

tramp -

  Another object of the invention is to provide a

  advanced RMST baking suitable for manufacture in a

  integrated circuit for use in a control system

of electric.

  Yet another object of the invention is to provide an RMST circuit having better performance in this respect.

  relating to transients present in the supply voltage

mentation.

  These and other objects of the invention are achieved in an electrical control system comprising an integrated circuit whose logic elements are to be placed in a predetermined initial state at the time of setting.

  under voltage In the control system, the voltage required

  integrated circuit (IC) is provided by a power supply

  tion, whose voltage increases at a lower speed than

  above a predetermined speed after putting into

  The original combination includes a circuit lying

  in the CI that includes at least one memory element connected

  to be fed between the first and second terminals

  integrated circuit (IC) power supplies, which are

  intended to be connected to the external power supply, the cir-

  cooked including the memory element having a terminal

  intended to preposition his state; and the restaurant circuit

2534751.

  power supply (RMST) on the IC The RMST circuit includes a conductive series circuit using

  integrable components and a connected door between

  first and second power supply terminals and operating at a voltage substantially equal to the supply voltage reduced by a lower voltage. The input of the door is

  connected to the output of the serial circuit The output of the

  forms the output of the RMST circuit and is connected to the positioning terminal of the circuit comprising a memory element The RMST circuit has an upper threshold and

  a lower threshold and it generates a pulse of preposi-

  when it becomes operational, and this impulse

  sion ends when the upper threshold is exceeded.

  first threshold is established in relation to the rate of increase of the voltage of the power supply, to let

  sufficient time for the restoration of the circuit

  the memory element at power up.

  According to a second aspect of the invention, the lower threshold of the RMST circuit corresponds to a supply voltage greater than or equal to the minimum voltage necessary for safe operation of the circuit comprising a memory element, and the difference between thresholds is established in relation to the minimum rate of increase

  tension, to allow sufficient time for the resi-

  tauration of the circuit including an element of memory,

  a momentary interruption of the supply voltage.

  In one embodiment, the circuit gate

  RMST is a hysteresis gate with two thresholds.

  In another embodiment, both a

  hysteresis gate and a semicon-

  driver (to switch off an element of the series circuit), in order to establish a difference between the thresholds. In another embodiment of the invention, the RMST circuit includes a semiconductor switching element that responds to the output signal of the gate by reducing the output voltage of the series circuit in relation to the power supply voltage. when a first threshold of

  the RMST circuit is exceeded, so as to produce a difference

  between the first and second thresholds of the RMST circuit.

  The rest of the description refers to the drawings

  appended which respectively represent: FIG. 1: a circuit diagram of an electrical control system comprising an integrated circuit having a

  possibility of "power-on restoration", used

  a CMOS manufacturing process;

  Figure 2: a series of idealized signals

  to the embodiment of the invention of the figure;

  Figure 3: a series of idealized signals

  the power-up restoration circuits shown in Figure 1 and Figure 3;

  Figures 4 and 5: two circuit diagrams of

  additional power-on restoration, also utilizing a CMOS manufacturing process; and

  Figure 6: a diagram of another restaurant circuit

  power-up using a process of

bipolar manufacturing.

  We will now consider Figure 1 which represents

  feels an electrical control system intended to put

  under load a complex charge, according to a temporal sequence

  determined by taking into account, conditions of the load and

  The system contains a circuit of res-

  power-up (RMST) 17, an RMST clock and hold circuit, 18, and a control logic circuit 16, all of which are incorporated into a circuit

  integrated control 11 The control IC controls the application

  charging circuit 12 of the energy from a

  alternative source at 120 V 50 Hz The RMST 17 circuit com-

  takes the two field effect transistors (TEC) Tl, T 2, 'and

  a hysteresis inverting gate SI At the initial application

  the voltage, the circuit of restoration to the setting

  voltage (RMST) 17 generates a restoration pulse which is transmitted to the clock and hold circuit of RMST, 18, which will be called, in abbreviated form, "H & M circuit". The H & M circuit comprises a circuit of FIG. 100 Hz clock, 19, which produces a digital signal at 100 Hz, a D flip-flop,

  FF 1, a RS type flip-flop, denoted by SR 1, and an invert-

  Under the effect of the application of the restoration pulse from the circuit 17, the H & M circuit 18

  generates a restoration pulse that initializes the

  control logic 16, and after the end of the restoration pulse, the flip-flop FF 1 is validated so as to

  count at a rate of 50 Hz The pulses at 50 Hz pro-

  from the circuit 18 are transmitted to the control logic circuit 16, which contains an N-stage counter and a

  combinational logic circuit The logic control circuit

  of initialized 16 produces a sequence of orders appearing under defined time conditions, which are directed

  to the power switching circuit 15 for triggering

  the charging sequence of the charging circuit.

  The elements of interest in the context of the invention are the original RMST circuit 17 and the inventive combination including the RMST 18 Clock and Hold circuit, for the purpose of ensuring that

  the control logic circuit 16 is correctly initiated

  and the internal counting starts, at the moment of the

power on.

  The electrical control system starting from

  120 V AC grid (not referenced).

  rence) includes a continuous supply of 155 V

  carries the bridge rectifier (DI, D 2, D 3, D 4); the condensation

  filtering filter Cl; a 7.6 V continuous supply Vdd, comprising the voltage drop resistor R 4, the zener diode 7.6 volts Zi and the filter capacitor C 4; charging circuit 12; The power switching circuit 15 and the control IC 11 The system also includes a low value resistor, R 6, which is used to provide timing information to the control IC. The 155-volt DC power supply, which receives its energy from the AC mains, is a simple power supply of the rectifier-filter type. The terminals of the AC rectifier input (D1, D2, D3, D4) are connected to the AC power supply The positive DC output terminal of the rectifier is connected to the positive terminal of the filter capacitor C1, which becomes the positive output terminal 13 of the DC power supply. The negative DC output terminal of the rectifier is connected. to ground of the system, which becomes the negative output terminal 14 of the continuous supply at 155 V The negative terminal of the filter capacitor C1 is connected to ground by the resistor R 6, and to the pad P 5 in the IC of low resistance value R 6 (0.0755 L) a

  a negligible effect on the action of the filter in the food

  continues, but provides synchronization information

  to the control IC Under normal load conditions

  the, a positive DC voltage of a nominal value of volts, but with a large undulation, appears on

  13 The average voltage and the percentage of corrugation

  depend on the energy that is absorbed by the loads

  12 The current flow path from the food

  Continuous voltage at 155 V closes via the charging circuit 12

  and the power switching circuit 15, which are

  symbolically in the form of circuits connected in series between the positive power supply terminal 13 and the system ground, 14 A wide arrow is used between the charging circuit 12 and the power switching circuit 15 to indicate one or more loads , who can be

  controlled by one or more switching elements.

  The use of a wide arrow between the charging circuit 12 and the control IC 11 is intended to indicate a-or

  several load sensing connections In a similar way

  As a result, the use of a wide arrow between the control IC and the power switching circuit 15 is intended to indicate one or more control connections.

  The continuous supply at 7.6 V is a power supply

  zener-diode-regulated single-mode, which is fed from the 155 V DC supply, using the resistor R 4 to reduce the voltage to a value suitable for the operation of an IC A terminal of the resistor R 4

  is connected to the cathode of the Zener diode Zi, and the

  output voltage of 7.6 V of the zener diode, which appears on the cathode of this diode, is filtered by the capacitor C 4 and is applied by the pad P 7 on the control IC to the bus Vdd on the integrated circuit The charging circuit of the 7.6 V supply is closed by the IC, because of the connection of the mass of the IC to the pad P 6, connected to ground

of the system.

  The integrated control circuit 11, which is

  In a highly simplified synoptic form, it performs the aforementioned control functions in the control logic circuit 16, which is part of the IC. As previously mentioned, the control IC is powered by the

  pads P 7 and P 6, and the potential Vdd is controlled by the circuit

  previously mentioned, the control IC receives the 100 Hz timing information from

  of the pad P 5 which is connected to the Clock circuit and the Main-

  RMST, 18 Circuit 18 then applies signals

  clock input and prepositioning to the logic circuit

  The control IC 11 also receives information regarding the state of the charging circuit, as represented symbolically by the wide arrow coming from the charging circuit 12, which enters the IC by unspecified pads and which passes directly to the load sensing terminal or terminals of the control logic circuit 16

  the effect of these input signals, the logic circuit of

  command commands the operation of the power switching circuit 15, as indicated by the wide arrow coming out of the

CI by unspecified pads.

  We will now describe the restoration operation

  power-up and the parts of the CI that cooperate with

  to the fulfillment of this function in the system

control shown.

  The control IC 11, which is divided to define the particular circuits 16, 17 and 18, uses a field-effect transistor (FET) technology of the

  complementary metal-oxide-semiconductor (CMOS).

  In the embodiment of FIG. 1, the RMST circuit comprises two TEC devices (TI, T 2) and a hysteresis inverting gate, SL. The RMST circuit is connected in the following way: the device Ti is a device p-channel and the device T 2 is an n-channel device, and both are connected with their main electrodes connected in series between the Vdd bus and the ground on the IC The TI device is a diode-connected wide-channel device (with for example 100/10 dimensions),

  which is proportionate so as to maintain a fall of

  significant voltage (1.2 1, s V) when connected in series with an appropriate impedance The source and the substrate of T1 are connected together with Vdd The gate and the drain are connected together with the node 20 to make the connection in diode, and the grilledrain electrodes are themselves connected to the drain of the NT channel device 2, which is a long channel device (having for example 10/100 dimensions), which operates in high value resistance incorporated on the chip The source and substrate of

  T 2 are connected to the IC mass, which completes the connection.

  xion series of two devices between Vdd and the mass of-CI-.

  The gate of T 2 is connected to the positive bus Vdd, for main-

  maintain a low level of conduction The output of the pair Tl, T 2, taken from the node 20, is connected to the input

  unique of the hysteresis gate Si.

  Each of the p-channel and n-channel devices (T 1, T 2) is represented by a long vertical line symbolizing the channel and by two short horizontal lines near the upper and lower ends of the "channel", symbolizing the source and drain An arrow drawn between the electrodes is directed away from the channel when the device is a p-channel device (N conductivity material in the channel), and to the channel when the device is an N-channel device ( conductivity p in the channel) The short vertical line to the left of the channel represents the insulated gate

  and is the input or control electrode of the device.

  In a p-channel device, the source and the drain are small P + diffusions in a doped substrate

  with type n, on which electro

  Because the source and drain can be reversed by inverting the polarization connection, in a device

  p-channel is conventionally called the "source" the con-

  tact which is polarized the most positively, while

  called the "drain" the contact that is polarized the least posi-

  The conduction between the source and the drain results from the creation of a p-channel in the n-type material immediately below the insulated gate. The conduction occurs when the gate becomes negative with respect to the source, with a deviation greater than the threshold of the device, this

  which allows conduction through the creation of major carriers

  (positive holes) between source and drain electrodes This is called "enrichment mode" operation. N-channel devices are formed in a larger box P which contains two n + regions provided with electrodes, respectively defining the source and the drain, and mutually spaced so that an insulated gate

2 534751

  can be applied to the region between the two diffusions As in the case of the p-channel device, it is also possible to invert the source and drain electrodes of an n-channel device. The source electrode is defined as the polarized electrode the most negatively, and the drain is defined as being the least negatively polarized electrode Conduction of the device is caused

  N-channel by applying to the grid a positive potential

  tif which creates majority charges (electrons) in channel n Conduction occurs when the positive potential applied to the grid, measured with respect to the source, exceeds

the threshold of the device.

  Although the particular circuits of the other parts

  CI parties have not been represented, it should be noted that they are

  all formed by the CMOS process, and that they are all

  The purpose of simplifying the presentation, the three main circuits 16, 17 and 18, which include the pernitent parts of the IC, have only been represented with the Vdd bus and they all share the IC mass. essential details The circuit 16 is represented without any internal detail; the circuit 18 is detailed to approximately logic level, with internal blocks represented by conventional logic symbols whenever possible; and the rest of the circuit 17 is detailed at the logical level, using here also a representation by

classic logical symbols.

  The RMST circuit 17 is completed by a hysteresis inverting gate (Schmitt trigger), Si, which switches

  to a second state when an input signal exceeds a first

  upper threshold, and which returns to the first state when the input signal falls below a second, lower threshold. Note that Si may take forms other than

  the one that is represented The elements of a hysterical door-

  If of appropriate type are shown in logical schema form They include NAND gates Nl I 101,

  ND 102 and ND 103 and the inverter I 101 More specifically, the por-

  NAND 101 is a three-input NAND gate whose three inputs are connected together and to the output node of T1, T 2. The output of ND gate 101 is connected to one of the two inputs of FIG. the two-input NAND gate, ND 102 An output port of the ND gate 102 is connected to an input of the NAND two-port NAND 103 The other NAND gate ND 103 is connected at the node of

  output 20 of Tl, T 2 The output connection of ND 103 is

  connected to the other input of ND 102 The output of ND 102 is

  connected to the input of the inverter I 101 The output of the inverting hysteresis gate Si (and of the RMST circuit 17) is

  connected to an entrance to the H & M 18 circuit, we will now

describe.

  As previously indicated, the RMST clock and hold circuit, 18, comprises the Hz clock circuit, 19, the FF 1 flip-flop, the RS SR 1 flip-flop, and the I-inverter 102. 100 Hz clock 19 is connected by the pad P 5 to the interconnection between Cl and 20.R 6 When the DC supply is energized, a charging current flows from the bridge diodes, crossing the capacitor Cl , and it returns to ground by the detection resistor R 6 The charging current is discontinuous, and it is interrupted when the polarity of the electrical network alternates and when a pair of diodes locks-while the other pair becomes conductive Because in a state of steady state, the flow of current occurs only when the rectified voltage exceeds the voltage

  instantaneous storage in the capacitor, the cir-

  charge current is further restricted and corresponds only to short intervals during which

  the capacitor absorbs a current from the electrical network

  to compensate for the more sustained current provided by the capacitor and directed to the load.

  periodic charging current contains clock information

  The clock circuit 19 uses a threshold amplifier such as that described in patent application US 393,696, filed June 30, 1982. The threshold amplifier operates under the control of data. analog that are provided by the

  current sensing circuit, to produce pulses

  digital output at twice the frequency of the power grid These 100 Hz digital pulses are

  applied to the clock input (C) of the flip-flop FF 1.

  The flip-flop FF 1 is a flip-flop of type D in which the output Q is retro-coupled to the input of

  data (D), while the output Q, on which appears

  clock pulses at 50 Hz, is coupled with the

  H & M 18 circuit output to the clock input of the circuit

  cooked control logic 16 The restoration input of the

  flip-flop FF 1 is connected to the output of the RMST circuit 17.

  As we will see, the signal of restoration brings back the

  FF 1 in the desired initial state, and keep it in this state until the termination of the RMST pulse. When the RMST pulse ends, the FFM flip-flop is released and

  can divide the input signal to 100 Hz to enable the output

  Q (and Q) which provides the 50 Hz clock signal which is

  applied to the control logic circuit 16.

  The RS SR 1 flip-flop and the I 102 inverter

  the two remaining logical elements in the circuit

  H & M 18 The SR 1 flip-flop has position inputs

  (S) and Restoration (R), which determine the

  two "locked" states of the Q output The SR 1 flip-flop

  takes two NOR or NR 1 and NR 2 gates An NR 1 input, which is the SR 1 restoration (R) input, is connected to the output of the RMST circuit 17 An NR 2 input, which is the Positioning input (S) of SR 1 is connected to the Q output of FF 1 The output of NR 1 is connected to the other input of NR 2 and the output of NR 2 is connected to the other input of NR 1, to establish cross-connect connections

  forming the flip-flop The output Q of the flip-flop SR 1 is connected

  by the inverter I 102 to the prepositioning input of the control logic circuit 16 As will be explained, when the RMST pulse appears, at the time of starting of the power supply, the two flip-flops FF 1 and SR 1 are restored to a state that restores and maintains the

  counter of the control logic circuit 16 in an initial state

  tial in which it does not count When the pulse of RMST ends, and when the counting at 50 Hz is triggered in the flip-flop FF 1, the flip-flop SR 1 is positioned at the moment of the appearance of the first pulse at 50 Hz on the Q output of FF 1, in a state that allows the properly initialized control logic circuit 16 to take its counting state and start the sequence of

control of the charging circuit.

  The RMST circuit and the H & M 18 circuit triggered

  together, the operation of the control logic circuit when Vdd begins to increase above zero.

  At the moment of the initial application of the voltage, the circuit

  control logic 16 is maintained in a pre-condition

  which prohibits sequential operation

  prohibition continues until Vdd exceeds a

  In other words, as long as the logic circuit on the IC is in the process of transitioning to specific output states (that is, when it becomes valid), then Vdd increases from zero, the output states of the RMST circuit 17 also become determined states, and in association with the

  H & M circuit, 18, they position and maintain the logic circuit

  16 is in the desired initial state until the first threshold of the Schmitt trigger is exceeded. Once the control sequence is triggered, it continues when the normal voltage Vdd is reached, until

  the end of the start-up sequence, and until the

  Cooked control logic goes into a final, static state.

  In the case where the voltage Vdd would disappear (either during the start-up sequence or after its completion), the RMST circuit (which continuously monitors the voltage Vdd) detects the moment at which Vdd decreases by crossing a second predetermined value. Vdd falls below the second value, the restoration circuit restores and

  maintains the control logic in the predetermined state.

  If Vdd increases again, the operation is at

  many similarities to that of a full reboot.

The operation of the RMST will now be described in more detail with reference to FIGS. 2 and 3. FIG. 2 is a graph showing seven signals useful for understanding the operation of the invention. It has been assumed that the designer has determined that the logic circuit belonging to a given CI structure requires a predetermined minimum supply voltage for the electronic components to work reliably, and that a predetermined duration is required after the elements of the logic circuit

  have become "valid", during which a pre-

  In this example, the nominal supply voltage is 7.6 V (Vdd), and the individual stages of the logic circuit become valid at the same time. about 1.5 volts The circuit as a whole will not work reliably at this value, but will do so at about 3 volts Under these conditions,

  the RMST impulse, which pre-positions and maintains the

  logic cooks in a predetermined initial state, must be

  present when the voltage falls below 3.5 volts.

  To meet this requirement, a hysterical gate is used.

  resis which indicates a power failure at 3.5 volts and a voltage of 4.75 volts (when the power is turned on) The designer has determined that a duration of

  -200 step, measured from the start (t), con-

  would come to guarantee the existence of a suitable duration for the initialization of the whole circuit, after the circuit became valid In the example considered, this delay is obtained by establishing a separate low voltage supply Vdd, with a separate filter having a predetermined maximum rise time for the characteristic giving Vdd On sets the rise time by selecting R 4

  C 4 with a margin of safety, considering a consump-

  the worst case) in the IC, and considering (as worst case) that t is a peak of the mains voltage

  With these assumptions, the charging time requires

  to reach the first threshold of 4.75 V must not be less than 50 fis A similar test (usually more severe) occurs for a momentary decrease in

  supply voltage, in the case where the supply voltage

  momentarily falls below 3.5 volts (the cutoff threshold) only, to increase again to 4.75 volts, ie the upper threshold.

  The time must also exceed 50 us. Characteristic values

  ticks taken with a safety margin are 0.022 p F

for C 4 and 27 k SL for R 4.

  The upper signal in the upper pair of

  signals in Figure 2 is the voltage Vdd plotted as a function of

  time, starting from start, which makes the hysteresis gate Si work, the trace ending after a momentary reduction of Vdd which makes it work again if the voltage at node 20 (i.e. Si entry) is traced in the company of Vdd, for the same suite

  In this example, the function value

  The Vdd voltage and the voltage at the node 20 increase and decrease together, the latter voltage having an operating value.

  6.1 volts, and remaining at approximately

  constant flow (eg 1.2 to 1.5 volts) below Vdd The following signal, below, is the output signal of NAND gate ND 102, inside the hyster gate. If this signal is subjected to a logical inversion by

  101 to form the output signal of the hysteresis gate

  If, drawn below it The output signal of the hysteresis gate SI is a pulse whose amplitude is limited by the available voltage Vdd to a value which is approximately 0.5 volts lower than Vdd L output pulse If starts when selected circuits take determined states (that is, become valid), which occurs at about 1.5 volts Using a common Vdd power supply, If not becomes invalid later than the circuits submitted to his command, and the process of

  Counting can be deleted from this point Supposed

  the highest threshold voltage of the hysteresis gate gives rise to tripping when Vdd reaches 4.75 volts, the time constant R 4 C 4 and the formed charge

  by the IC determine the shortest duration

  the threshold that terminates the output pulse of Si.

  Figure 3 illustrates the factors that set the voltage at which the SI output pulse ends during power-up. In a hysteresis gate, the thresholds depend on Vdd, and are in fact a percentage.

  almost constant of Vdd, the upper threshold being a fraction

  approximately constant Vdd (eg 0.63 to

  0.75 Vdd), and the lower threshold being an approximately

  a constant Vdd constant (eg 0.38 to 0.50 -Vdd).

  The upper trace in FIG. 3 represents Vdd, with the voltage in ordinate and the time in abscissa, and with nonlinear graduations to make linear the plot of

  Vdd The upper threshold of Si follows this proportional relationship

  tionality and has been mapped out on the assumption of a

  0.75 In the embodiment of FIG. 1, in which V 20 is about 1.5 volts lower than Vdd, the upper threshold is crossed at t 2, and the output pulse of

  If then ends If the voltage at node 20 was lower

  than Vdd of a value equal to two diode voltage drops, as in the embodiment of Figure 4, the

  threshold would be crossed in t 3, giving a longer impulse.

  If we suppose that the first impulse of Si is 50 ls, the second can be 125 juices (assuming that other conditions are

remain the same).

  The value of Vdd at which the upper threshold appears can be calculated as follows VH = 0.75 Vdd Vdd Vgs 1 by designating by Vgs 1 the voltage drop in TI, and

assuming a fraction of 0.75.

  The resolution of this equation gives: Vdd = 4 Vgs Assuming Vgs 1 = 1.5 volts, the calculated upper threshold appears at 6.0 volts. In fact, the threshold appears at 4.75 volts, which is mainly due to the fact that the fraction is closer to 0.63 A similar approximation of the lower threshold can be similarly calculated, with similar results, assuming that the lower threshold can be calculated using a fraction of 0.5 VL = 0, 5 Vdd Vdd Vgs 1 When solving, we obtain Vdd = 2 Vgs 1 Assuming Vgs 1 = 1.5 volts, the lower threshold

calculated appears at 3.0 volts.

  The actual threshold actually appears at 3.0 volts.

  The TEC T 2, acting as resistance, must be forward biased to absorb current from T 1, to ensure proper operation. This is done by connecting the gate of T 2 to Vdd Vds 2 = Vdd Vgs 1 Vgs 2 = Vdd This leads to the unblocking of T 2 when Vdd is

greater than about 1.5 volts.

  Referring now to the graphical representations of FIG. 2, the output pulse SI actuates the flip-flop SR 1 which applies to the control logic circuit the "prepositioning" pulse which is represented below the output pulse of S1. The output pulse of IF releases flip-flop FF 1, and the 100 Hz clock, which is active, applies a clock signal to FF 1, which in turn produces a 50 Hz clock signal for the control logic circuit 16 (The two clock signals are represented with a time scale much more contracted than that

  start-up transients, as indicated by the

  time) When the first clock pulse at Hz sets FF 1 to zero, a positioning signal from

  the output Q of FF 1 is transmitted to the input 51 of the bascule

  At this time, the output of SR 1 takes a "positive" state.

  "and the control logic circuit, which has now been

  naked in this state, is released.

  If the voltage Vdd momentarily decreases, as shown in the right part of the graph of FIG. 3, the hysteresis gate produces a pulse at t 4, when its output signal falls below the lower threshold Si

  (in the worst case), the voltage increases immediately

  diatement, the restoring pulse of Sl which has just been triggered in t 4 ends in t 5 The minimum duration (between t 4 and t 5) for the restoration pulse is established in this case by the difference between these thresholds This condition imposes the existence of a hysteresis in the RMST circuit (ie a difference between the upper and lower thresholds), as well as the value of this difference. graph, the

  duration of the pulse is reduced by about 30% in the con-

  most unfavorable transitional

  If you want a bigger hysteresis

  (greater separation between the upper and lower

  the figures can be used

  4 or 5 In these embodiments, which utilize a

  hysteresis as in Figure 1, an additional diode

  D1 in FIG. 4 (or a diode-connected TEC T 4 in FIG. 5) is added, and is connected in series with Tl and T 2 between Vdd and ground. An additional TEC (T 3) is interposed in FIGS. two embodiments in parallel

  the on Dl (T 4), with its gate connected to the output of Si.

  When the TEC T 3 leads, it eliminates Dl (or T 4) in the

  short-circuiting, which raises the division ratio

  voltage voltage at the input of Si As shown in FIG. 3, the upper threshold is increased by the drop at the terminals of D1 (or T4), and the restoration pulse of Si is lengthened since the time between 1 and t 2, up to the duration between t 1 and t 3 (for the embodiment of FIG. 4), as shown in FIG. 3 Vdd Vgs VD = V The lower threshold remains practically the same as in FIG. first embodiment Vdd Vgs = VL The embodiment of FIG.

  a slightly longer duration for the restoration impulse

  because of the "substrate effect" of T1, since the p-box of T1 is connected to Vdd. If desired, this effect can be eliminated by using an N channel for Tl, and by connecting its p-box at its source As indicated above, the transistor T 3 derives the excess voltage, once the switching point has been reached, and does not significantly affect the lower threshold With a given product R 4 C 4 and a given hysteresis gate, the two modes of

  Figure 4 and Figure 5 increase nota-

  the duration of the Si restoration pulse -

  The duration of 50 Fis for the output pulse of Si

  is a choice with a margin of safety for the function

  positioning and maintenance in the practical application

  In the circuit shown in FIG. 1, the duration could be substantially reduced by the fact that it is essentially established by the requirement of reaching states.

  desired initials for FF 1 and NR 1 of SR 1 (when Vdd increases

  te from zero) The control logic circuit 16 dis-

  several additional milliseconds, because the output signal of the H & M circuit appears on the next 50 Hz output signal of FF 1 This additional time guarantees a correct prepositioning of the control logic circuit 16 However, it is not possible to determine exactly the duration of the Si pulse, during start-up, from conventional nominal values, since the response times of the circuits are usually defined

  for the full value of Vdd Delays are usually

  considerably longer when Vdd is less than

  nominal value, and this uncertainty leads to

  ser it is better to make a mistake in the direction giving the SI output pulse a larger value

as necessary.

  Although the power-up recovery circuit has been represented in an optimal form, it should be noted that the illustrated series circuit may take other forms. For example, the diode-connected wide channel TEC

  (Tl), connected in series with a long-channel and

  high voltage (T 2), between the Vdd bus and the earth, and which provides for the hysteresis gate an output voltage which is always less than a constant value at the voltage

  power supply (Vdd), can be replaced at the price of a

  some performance degradation, through a divisional network

  of tension that gives for application to the hysterical door-

  has a voltage lower than Vdd (and proportional to

thereof).

  Figure 6 shows an additional variant of the power-on restoration circuit.

  6, there is a combination of a diode D 2 and a transistor

  switching tor (T 6), intended to increase the hysteresis, which modifies the setting of the voltage division at the input of the "gate" circuit comprising the transistor T 5 It is not necessary that the RST circuit has means other than those provided by this combination, to separate

  the upper threshold of the lower threshold.

  FIG. 6 further shows a bipolar embodiment of the RMST circuit. The output of the gate T 5 goes low when the supply voltage (Vcc) reaches a point at which the series diodes lead with a current level. high enough to bias T 5 in forward direction The voltage at which this switching occurs is dependent on the value of R1 (which is normally high, for example 50 kf L), and typically occurs when Vcc exceeds 2.25 volts The transistor T 5 can not be fully conductive when the output of the network, at the collector of T 5, goes to ground, until the PNP transistor T 6 also becomes conductive, which raises the first threshold of a value equal to a diode voltage drop, when the upper diode D 2 is short-circuited This is a normal operating condition, with T 5 and T 6 conductors, and the output voltage

  when the voltage Vcc is reduced, the output voltage

  tie goes to the "high" level, when Vcc falls below

  1.5 volt The lowered threshold is due to the fact that D 2 is effectively

off the circuit.

  In order for the power-up restoration circuit to be effective, it must apply a reset pulse while the memory elements reach a known valid state. This requires that the SI-hysteresis input signal be low for that the circuit

  logic becomes valid This low state is established by the

  of the grounding device T 2, in the circuit

cooked series Tl T 2.

  Once Vdd exceeds Vtn (the threshold voltage of the n-channel device) during the voltage rise, T 2 becomes conductive, causing the node 20 to go low. The node 20 will remain in the low state until it is brought to the high state by Tl Because of the connection

  diode, Tl, the latter will begin to

  when Vdd will exceed | Vtpl (threshold voltage of the dis-

  p-channel positive) For any level of Vdd greater than I Vtp |, the node 20 will be at a voltage level at which the current from Tl opposes the T 2 Du low booster effect. Since Tl can supply a much higher current than T 2, node 20 will tend to

  follow Vdd very closely, at a threshold level below.

  In the unlocking region, that is when

  Vdd is close to i Vtpl, the weak diode effect due to

  weak rants causes some rounding of the p-channel threshold. This can be seen by examining a characteristic of TEC for Vgs = Vds.

  of Vdd = 1 Vtp |, some additional capacity is available

  effective reminder to the low level, since

It is not highly conductive.

  Since the node 20 is also the input of the hysteresis gate Si, as indicated, the voltage at the node must be low when Si becomes valid. In the embodiment of FIG. 1, the upper threshold of Si is not not well defined when Vdd is low So, this mode

  realization requires lVtp 1> Vtn to work well.

  For technologies with Vtp | C Vtn, it is necessary to have a hysteresis gate with a higher threshold

  sufficiently higher than Vdd / 2, when Vdd increases by

  I Vtp I shot To avoid this complexity, we can use

  a door with hysteresis more classical with modes of

  such as those in Figures 4 and 5.

  In the embodiments of Figures 4 and 5, additional serial elements were added between Vdd and the node. Initially, the voltage at node 20 remains unknown until Vdd exceeds Vtn. At this time, node 20 is fired. to the low state due to the conductivity of T 2 However, nothing pulls the node 20 to the high state until the voltage Vdd is high enough to pass to the conductive state all devices that are

  above the node 20 In the case of the mode of

  4, this level of Vdd is the sum of the bipolar diode threshold (about 0.5 -0.6 volts for very low currents) and the threshold of TI (I Vtp I plus the rear gate effect / substrate due to voltage of 0.5-0.6 volts

  between the source and the substrate) In the case of the mode of

  5, the level of Vdd is the sum of the voltage Vtp of T 4 and the threshold of Tl (I Vtp I plus the substrate effect due to the voltage drop across T 4). that this level of Vdd is reached, the voltage acts as it does in the embodiment of FIG. 1, that is to say that it follows at a level presenting a difference

  relatively fixed below Vdd, which tolerates a

  This causes the input signal of Si to be known and appropriate when Si becomes valid (even in

the case where lVtp | = Vtn).

  Once Si changes state (and the RMST is over), T 4 eliminates the extra device. This makes these circuits work just like the mode

  embodiment of Figure 1 during a power failure.

  The end result of this is that the Vdd level

  the voltage of the node 20 begins to rise is increased

  ted, and additional hysteresis is added to the func-

global organization.

  The door Si which is shown in FIG. 1 is a particular hysteresis gate made from a set of NAND gates forming an economical and efficient two-threshold gate, the thresholds of which are proportional.

  This is a practical choice, but we can easily use

  other structures Although we have shown a door to

  particular CMOS hysteresis (Figure 1) and a

  bipolar systems (Figure 6), it is obvious that we can use

  other threshold digital circuits, provided, of course, that they have the essential low Vdd operating characteristics mentioned above, and that they produce a digital output signal. The threshold circuit may include operational amplifiers and

  comparators, in addition to doors and

selective mission classics.

  The series circuit considered here that is used

  to produce at node 20 the output signal which is applied

  That the gate is preferably integrable and nonreactive, and it establishes a conductive path between Vdd and ground. The components used herein may include semiconductor devices (including diode connected devices), semiconductor diodes, and the like. / or resistances

  that can be incorporated into an IC.

  The RMST circuit is of interest not only

  to initialize a CI at power-on,

  where all important functions are incorpo-

  in the considered CI, but also to initialize-a

  CI on power-up in case of signals coming from

  This would be the case, for example, when the IC considered receives signals from

  of a microprocessor In general, the order from the micro-

  processor is not continually emitted, but is issued once and "stored" in the CI command register If the microprocessor has a fault at power up, it is important that the power to the IC In the case of a motor controlled by a CI, it would be important for the CI associated with the motor to be initially placed in the "off" fault condition if a fault condition is known and has a safety character. the microprocessor was defective A motor that is switched on and can not be controlled is obviously dangerous, and the RMST circuit can be used to initialize the state of the control logic circuit.

  to guarantee a safety condition.

  In the preferred embodiment, the low voltage DC power supply for the integrated circuit receives its power from a higher voltage DC supply. The higher voltage supply is designed to provide power to the load circuit, either

  characteristic 100 W under a current of an ampere

  The lower voltage voltage must only provide the energy required for the integrated circuit, which frequently corresponds to a current of the order of 10 m A. When the higher voltage supply is switched on, the rise time

  the output voltage depends on the phase of the alternating wave

  tive at the instant of connection to the DC supply, the value of the filter capacitor (Cl), the tolerable internal impedance of the virtual generator, and the load impedance These rise times are often too long in the

worst case.

  The desired minimum progressive increase in the voltage Vdd that is applied to the control circuit can

  thus usually be obtained in the best conditions

  by the use of a separate RC power supply, as shown here, in which the value of the series resistance R 4 can be easily selected as that of the filter capacitor C 4, to obtain a desirable progressive increase of Vdd. of 27 kf (R 4) and

  0.022-li F (C 4) were chosen to optimize other factors.

  they are suitable for minimum delay

  more than 50 lilies required here.

Claims (8)

  1 Electric control system including a   integrated circuit (11) of which a plurality of logical elements   to be set in a predetermined initial state at the time of power-up, the energy required for this integrated circuit (IC) being provided by a power supply   (R 4, C 4) whose voltage (Vdd) increases at a rate of   predetermined at the time of power-up, which is   characterized in that it comprises: (A) first (P 5) and second (P 7) terminals on the integrated circuit (IC) for connection to the external power supply; (B) a circuit (16) in the IC, including at least one memory element connected between the first and second power terminals, for being powered, which circuit has a terminal for setting its state; and (C) a power-up reset circuit (RMST) (17) on the IC, which comprises: (1) a series circuit (Tf, T 2) forming a conductive path between the first and second terminals of power supply (P 5, P 7)   and entering into operation at a voltage which is practically   the same as for the circuit comprising-a memory element (16), so as to provide an intermediate voltage (V 20) equal to the decreased supply voltage (Vdd)   a lower voltage; and (2) a digital threshold circuit   that (SI) forming a nonreactive conductive path between the first and second supply terminals (PS, P 7) and incoming   in operation at a supply voltage which is practically   the same as that of the circuit comprising an element   of memory (16) whose input is connected to the output (20) -   the series circuit (T1, T 2), the output of this threshold circuit forming the output of the RMST circuit, and being connected to the positioning terminal of the circuit comprising a memory element (16); and the RMST-circuit (17) having an upper threshold and a lower threshold and producing when it enters into operation a prepositioning pulse that terminates when the upper threshold is exceeded, while the first threshold is established in relation to with speed   to increase the voltage, to allow enough time to   circuit for recovering the circuit comprising a memory element (16) at the time of power-up. System according to Claim 1, characterized   in that the lower threshold of the RMST circuit (17) corresponds to   to a supply voltage (Vdd) greater than or equal to the minimum voltage necessary for safe operation of the circuit including a memory element (16), and the difference between the thresholds is established in connection with the rate of increase of the tension, to leave a time   sufficient for the restoration of the circuit including a   memory during a momentary interruption of the supply voltage (Vdd).   3 System according to claim 2, characterized in that the digital threshold circuit (Si) of the circuit of   RMST (17) is a hysteresis gate with two thresholds.   System according to Claim 2, characterized in that the RMST circuit (17) comprises a semiconductor switching element (T 3) which reacts with the signal of   digital threshold (IF) output by reducing the   output voltage of the series circuit (Tl, T 2) in relation to the   supply voltage (Vdd), when a first threshold of the cir-   cooked from RMST (17) is exceeded, to create a difference between   the first and second thresholds of the RMST circuit.   System according to claim 2, characterized in that the digital threshold circuit (Si) of the RMST circuit (17) is a hysteresis gate having two thresholds, and the   The RMST circuit comprises a semicon-   driver (T 3) which responds to the output signal of the gate (Si) by reducing the output voltage of the series circuit (T1, T 2) in relation to the supply voltage, when a first threshold of the circuit of RMST (17) is exceeded, to increase the difference between the first and second thresholds of the RMST circuit. System according to Claim 2, characterized in that the lower voltage of the series circuit (Tl, T 2) is practically constant.   System according to Claim 6, characterized in that the digital threshold circuit (Si) is a gate whose thresholds are substantially fixed fractions of the voltage. power supply (Vdd).   8 System according to claim 7, characterized in that the lower voltage of the series circuit (T1, T 2) corresponds to the voltage drop of a circuit element   semiconductor (T1) in the conductive state.   System according to claim 7, characterized in that   the serial circuit comprises a first circuit element   semiconductor (Tl), a diode (D1) connected to provide a substantially constant voltage, corresponding to said lower voltage, and a second circuit element to   semiconductor (T 2) with high impedance.   System according to claim 9, characterized   in that the door (SI) is a hysteresis door.   System according to Claim 2, characterized   in that the external power supply comprises: (1) a power supply   continuous higher voltage (14); and (2) a food   continuous lower voltage supply (R 4, C 4, ZI) which is fed by the continuous supply of higher voltage and   which has an output voltage (Vdd) that is suitable for the function   of the IC (11), this lower voltage supply   comprising a voltage drop resistor (R 4) and a filter capacitor (C 4) selected to provide a sufficiently low output voltage increase speed to restore the circuit including memory element (16).   System according to Claim 11, characterized   in that the continuous supply of lower voltage   takes a zener diode (Zl) connected in parallel to the con-   filtering densifier (C 4) and having a suitable value for the operation of the IC (11).