JPS5994925A - Integrated power on reset circuit for electric controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an electrical control device, and more particularly, to an electrical control device that resets to an initial state when power is applied or when power is interrupted and reapplied. The present invention relates to an electrical control device that performs control by means of a logic element including a memory device in which it is necessary to store and hold data. Furthermore, the invention relates to an electrical control device in which the control logic is in an integrated circuit.

DESCRIPTION OF THE PRIOR ART The present invention addresses the problems associated with electrical control devices having storage elements that tend to go into random states and generate undesired control commands when power is first applied. There is. The present invention deals with means for ensuring that the initial state of the storage element as described above is obtained when power is first applied or temporarily interrupted. This feature is.

This is generally referred to as the power-on reset (FOR) function.

In the so-called dynamic type conventional power-on-reset circuit, the voltage division between the resistor and the capacitor is detected and the I
It had been determined that C was turned on. For example, if a capacitor is connected to ground and a resistor is connected to a power supply (Vdd), then the RC connection points are at ground potential, and at some slow rate the power supply voltage (Vdd) is
rise to First ``0'' state and last $11 #
The delay time between states provides an initialization period sufficient to reset all storage elements to a known, proper initial state.

In conventional circuits, the positive supply voltage (Vdd) is
When turning on one circuit, FO increases in a slower manner than the voltage on the capacitor of the R circuit.
The R circuit may not work. In this case, the input to the gate sensing this voltage is not particularly reduced (Vdd
, the input to the gate goes high (ie, u 1 t'') prematurely, switching off the voltage-sensing gate before it can effectively protect one circuit. If the positive power supply voltage (Vdd) increases more rapidly than the voltage of the capacitor of the FOR circuit when the circuit is turned on, as long as this condition continues, the FOR circuit will operate at turn-on;
If the supply voltage is abruptly interrupted for only a short period of time, the Ic that the FOR circuit's capacitor discharges is too small.

The FOR circuit ignores this transient, which disturbs the state of the storage device. In summary, dynamic PAR circuits that rely on sensing voltage Vdd by a voltage divider between a resistive element and an actance element (in this case, a capacitive element) are not fail-safe under worst-case conditions. be. Therefore, the present invention uses a so-called "static JPOR" circuit, and senses Vdd by a conductive, non-reactive element that does not depend on the rate of change of voltage.

It is desirable that the FOR circuit be compatible with integrated circuit configurations widely used in control devices.

In this application, it is desirable that the FOR circuit uses no non-integrable components and has a minimum number of pins, preferably no pins, connecting the IC to the rest of the control device.

[Summary of the invention]

Accordingly, it is an object of the present invention to provide an improved power-on-reset (FOR) circuit for use in electrical control systems.

Another object of the invention is to provide an improved FOR circuit suitable for integrated circuit configurations used in electrical control equipment.

Yet another object of the present invention is to provide a FOR circuit with improved performance against power supply voltage transients.

To achieve these and other objects of the invention,
An electrical control device is provided that includes an integrated circuit (IC) that must set its logic elements to a predetermined initial state upon turn-on. In this control device, power for the IC is supplied by an external power supply, the voltage of which increases rapidly below a predetermined speed after turn-on. The novel combination of the present invention uses an integrated circuit (IC) for connection to an external power source.
A memory element built-in circuit on an IC including at least seven memory elements connected to be supplied with power between first and second power supply terminals provided on the IC.

and a power-on reset (FOR) circuit on the IC. The memory element built-in circuit has a terminal for presetting its state. A FOR circuit includes a conductive series circuit using components that can be integrated and a gate connected between first and first power supply terminals and operating at a voltage substantially equal to the power supply voltage less a voltage. have.

This gate has its input connected to the output of the series circuit.

The gate forms the output of the FOR circuit and is connected to the set terminal of the circuit with built-in storage element.

The FOR circuit has a relatively high threshold and a relatively low threshold, and generates a preset pulse when the higher threshold is exceeded. Terminate the pulse. This first threshold value is set in relation to the voltage increase rate of the power supply so that sufficient time is obtained to reset the storage element built-in circuit at turn-on.

According to the first aspect of the present invention, the lower threshold of the PAR circuit corresponds to a power supply voltage that is equal to or higher than the minimum voltage necessary to reliably operate the circuit with a built-in memory element, and
The threshold opening difference is set in relation to the lowest voltage increase rate so that sufficient time is available to reset the storage element built-in circuitry during a temporary interruption of the power supply voltage.

In one embodiment, the gate of the FOR circuit is a hysteresis gate with two thresholds.

In other embodiments, hysteresis gates and semiconductor switches (to isolate elements of a series circuit) are used to set the threshold opening difference.

In another embodiment, the FOR circuit is responsive to the output of the gate to reduce the output voltage of the series circuit with respect to the power supply voltage when the first threshold is exceeded to reduce the output voltage of the series circuit with respect to the supply voltage.
and a semiconductor switch forming a difference between the second threshold value and the second threshold value.

The novel and distinctive features of the invention are pointed out in the appended claims. However, the invention, together with other objects and advantages, may be better understood by reference to the following description and accompanying drawings.

[Description of preferred embodiment]

Referring to FIG. 1, an electrical control system is shown that provides power to a composite load in a predetermined time sequence taking into account load and power line conditions. This device is powered on.
Reset (FOR) circuit 17, clock and (POJ
Holding circuit 18. and a control logic circuit 16, all of which are provided on the control integrated circuit (IC) 11.

The control IC controls the supply of power to the load circuit 12 from an AC power supply of /e2θV, ≦θHz. P.

R circuit 17 has one FET element TI, T2 and one inverting hysteresis gate S1.

First, when power is supplied, the power-on reset (
FOR) circuit 17 generates a reset pulse which is connected to the clock and P.

It is supplied to the R hold (C-H) circuit 18. The C-H circuit generates a 2θHz digital signal at 20H.
z-timing circuit 19, clock-operated data flip-flop FF1, and set/reset latch SR
1 and an inverter 1102. FOR
When a reset pulse is applied from circuit 17, C-H
Circuit 18 generates a reset pulse that initializes control logic circuit 16.

After the end of this reset pulse, the flip-flop FF
i can be counted at a rate of 1QHz. C-H circuit 1
The θHz pulse from 8 is coupled to a control logic circuit 16Vc having an n-stage counter and a combinational logic circuit.
The initialized control logic 16II'i generates a series of timed commands that are sent to the power switching circuit 16 to begin the sequence of powering the load circuits.

Key aspects of the invention include the novel FOR,circuit 17 and clock and FOR retention to ensure that the control logic 16 is properly initialized and internal counting begins when power is applied. The combination includes circuit 18.

/20V main AC line (not marked) The electric control device is connected to the bridge rectifier (Dl, D2
．． D3. D4 ) and filter capacitor C1
/3-jV DC power supply having voltage drop resistor R4 and 71. 7V DC Vdd with Zener diode Z1 of volts and filter capacitor C4
Power source, load circuit 12, and power switching circuit 15
and a control IC1l. In addition, control I
A small value resistor R6 is provided which is used to provide timing information to C.

An Ovolt DC power supply that receives power from an AC line is a power supply with a simple rectifier-filter configuration.

AC input terminals of the bridge rectifier (Di, D2.D3.D4) are connected to the AC line. The positive DC output terminal of the rectifier is connected to the positive terminal of filter capacitor C1, which is the positive output terminal 13 of the /3jV DC power supply. The negative DC output terminal of the rectifier is connected to the ground of the control device, which is the negative output terminal 14 of the /jjV DC power supply. The negative terminal of the filter C1 is connected to ground via a resistor R6, and is connected to the pad of the control IC.

P5 (meaning a terminal provided on an integrated circuit). The small value (θθ2!Ω) of the resistor R6 is negligible with respect to the filtering effect of the DC power supply, but it provides timing information to the control IC. Under normal load conditions, nominal /! ! A positive DC voltage in volts but with substantial ripple appears at terminal 13. What is the average voltage and ripple ratio?
It depends on the power consumption of the load 17. /! ! ■The current path from the DC power supply is between the positive power supply terminal 13 and the 7-south 14 of the device.
is completed through a load circuit 12 and a power switching circuit 15 which are connected in series between. The wide arrow between load circuit 12 and power switching circuit 15 is used to indicate more than seven loads that can be controlled by more than seven switches. Connections that sense more than seven loads are indicated using wide arrows between the load circuit 12 and the control IC 11. Similarly, more than seven control connections are indicated using wide arrows between the control IC1i and the power switching circuit 15.

The 7V DC power supply used resistor R4 to reduce the voltage to a value appropriate for IC operation. This is a power supply that is adjusted using a simple Zener diode that is supplied from a DC power supply. One terminal of resistor R4 is connected to the cathode of Zener diode Z1. The Zener output voltage of Z volts appearing at this cathode is smoothed by a capacitor C4 and connected to the Vdd bus of the integrated circuit via a pad P7 of the control IC. The 7V load circuit is completed by passing through the inside of the IC and then connecting to the device's ground via a pad P6 which is then connected to the IC's ground.

The control integrated circuit 11, shown in a highly simplified block diagram, is adapted to perform the control functions described above within the control logic circuit 16 of the IC.

As described above, the control IC receives power between pads P7 and P6, and the voltage Vdd potential is monitored by the POR circuit 17. The control IC is from pad P5 to 7.2
Receive 0Hz timing information. Pad P5 is
It is connected to the clock, FOR, and holding circuit 18. This circuit provides a clock input and a "preset" input to control logic circuit 16. The control IC 1i also receives information about the state of the load circuit as indicated by the wide arrow from the load circuit 12 (this is input to the IC via a pad not shown); It is applied directly to the load sense terminal of control logic circuit 16. In response to this input, the control logic circuitry controls the operation of the power switching circuitry 15, as indicated by the wide arrow from the IC via a pad not shown.

The portions of the IC that perform the power-on reset operations and functions of the illustrated controller will now be described.

The control IC 11, which is divided into specific blocks (16, 17 and 18), is composed of complementary metal/oxide/semiconductor (
0MO8) field effect transistor (FET) technology. - In the embodiment of Figure 1, the FOR circuit consists of two FETs
Elements (T1, T2) and inverted hysteresis number gate S
1. This FOR circuit is connected in a first order manner. Device T1 is a p-channel device and device T2 is an n-channel device, both connected in series with their main electrodes between the Vdd busbar of the IC and ground. When element T1 is connected in series with a suitable impedance, the voltage drop is (/2-/!V)
allocated to maintain the It is a diode-connected wide channel (for example /θθ/10) element.

The source and substrate of device T1 are connected to the Vdd bus, the gate and drain are connected together at node 20 to create a diode connection, and the gate-drain electrode is connected to the drain of n-channel device T2. There is. This element T2 has a long channel (e.g. /θ//θθ) that acts as a large value on-chip resistor.
It is an element of The source of element T2 and the substrate are connected to the IC ground, thus connecting the Vdd bus and the IC
The two elements are connected in series between the ground and the ground.

The gate of element T2 is connected to the positive Vdd bus to maintain a small level of conduction. Connection point 20
The outputs of the pair of elements T1 and T2 are connected to a single input of a hysteresis gate S1.

p-channel device and n-channel device (T1.T2
) are indicated by a long vertical line representing the channel and λ short horizontal lines near the top and bottom of the channel representing the source and drain electrodes, respectively. The arrow between the electrodes indicates that the device is a p-channel device (
When the channel is an n-conductivity type material), the direction is directed out of the channel, and when the device is an n-channel device (
When the channel is a p conductivity type material), it points toward the channel. The short vertical line to the left of the channel indicates the insulated gate, which is the input or control electrode of the device.

In a p-channel device, the source and drain are n
There is a small P diffusion region within the type substrate.

Electrodes are attached to them. The source and drain may be reversed by reversing the bias connections, and in p-channel devices this is usually the case.
The most positively biased connection is called the "source" and the least positively biased connection is called the "drain."

The conduction between the source and drain is the n
This is caused by the induction of a p-channel in the type material. Conduction occurs when the gate becomes negative with respect to the source above the threshold of the device.

This is a majority carrier (hole) between the source and drain electrodes.
This is due to the fact that it is generated. This is called "enhancement mode" operation.

In an n-channel device, λ n10 diffusion regions each forming a source and a drain are provided in an n-type material, and an insulated gate is provided on a region between the two.

It is formed by providing electrodes in the n0 area.

As with p-channel devices, the source and drain of n-channel devices may be reversed.

The source electrode is defined as the more negatively biased electrode and the drain electrode is defined as the less negatively biased electrode.

An n-channel device is turned on by applying a positive potential to the gate and inducing a large number of charges (electrons) within the n-channel. Conduction occurs when a positive potential applied to the gate relative to the source exceeds the threshold of the device.

Although the specific circuits of other parts of the IC are not shown, it will be understood that they are all formed using the CMO8 manufacturing process, draw power from the Vdd bus, and have a common ground for the IC. To simplify the drawing, the three main blocks (16, 1? and 18) containing the relevant parts of the IC are shown in only the main parts in detail. The internal details of circuit 16 are not shown, circuit 18 is shown as a logic circuit with internal circuitry represented by conventional logic symbols, and the remaining circuit 17 is represented by one conventional logic symbol. Illustrated with a diagrammatic logic circuit.

The PAR circuit 17 has one-inversion (Schmitt) hysteresis.
It also has a hysteresis gate S1 which causes a second hysteresis gate to open when the input exceeds a first relatively high threshold.
state and returns to the first state when the input falls below a second relatively lower threshold. It will be appreciated that gate S1 may take other forms than that shown.

The elements of a suitable hysteresis gate S1 are shown in logic diagram form. This is NAND gate NDIO1
, ND102 and ND103, and an inverter 101. For more information, please refer to Nand Gate NDIO
I is a 3-boat Φ NAND gate with three input ports connected to each other and to the output connection point 20 of elements T1°T2.

The output of gate ND 101 is connected to one of the two inputs of a valid NAND gate ND102.

One output connection of NAND gate ND102 is 62
It is connected to one input of the boat NAND gate ND103. The other input of the NAND gate 103 is
It is connected to the output connection point 20 of elements TI and T2.
The output of NAND gate ND103 is NAND gate ND
102. The output of NAND gate ND102 is connected to the input of inverter 101. The output of the inverting hysteresis gate 81 (and the FOR circuit 17) is connected to the input of a C-H circuit 18, which will be described later.

As mentioned above, the clock and FOR holding circuit 18 includes a /e;2θHz timing circuit 19, a flip-flop FF1, a set/reset latch SRi, and an inverter 02.

/, 20Hz timing circuit 190 input is connected to the interconnection point between elements C1 and R6 via pad P5. When DC power is supplied, capacitor C1
A charging current flows from the bridge rectifier through R6, which flows to ground through sensing resistor R6. This charging current is discontinuous, alternating the polarity on the line and interrupting when one pair of diodes becomes non-conducting and the other pair of diodes becomes conductive. In steady state, the current flow occurs only when the rectified voltage exceeds the instantaneous voltage stored in the capacitor, so the charging current flow is further reduced.

Current is limited to a short period of time during which the current flows from the line to the capacitor in order to provide more sustaining current to the load from the capacitor. This periodic charging current therefore contains precise timing information of the line frequency.

As the timing circuit 19, a threshold amplifier as described in US patent application Ser. The threshold amplifier operates in response to analog data provided by the current sensing circuit to generate digital output pulses at twice the line frequency. This 72θHz digital pulse is the clock (C) of the flip-flop Ii”Fi.
Connected to input.

Flip-flop FFi is a data clock operated flip-flop whose Q output is:

The Q output, which is connected to the data (D) input and where a clock pulse of θHz appears, is connected from the C-H circuit 18 to the clock input of the control logic circuit 16. The reset (R) input of flip-flop FF1 is FOR, circuit 1.
It is connected to the output of 7.

This reset signal returns the flip-flop FFi to the desired initial state, and this state is maintained until the pulse from the FOR circuit ends. When the pulse from the PAR circuit ends, the flip-flop FFl is opened and /
, divide the input of 20H2.

The Q (and Q) outputs are activated to generate a 1QHz clock that is supplied to control logic circuit 16.

Set/reset latch SR,1 and inverter 102 constitute the remaining two logic elements of C-H circuit 18. Latch SR1 has separate set (S) and reset (R) inputs.

Determine the two latch states of these input uQ outputs.

Latch 5RIl/'i1.2 people Kanoa Gate NR1
and NR2. Resetting latch SR1 (
R) One input of the NOR gate NR7 is F
It is connected to the output of the OR circuit 17. latch 8Ri
One input of NOR gate NR2, which is the set (S) input of , is connected to the Q output of flip-flop FFi.

The output of NOR gate NR,l is connected to the other input of NOR gate NR,2, and the output of NOR gate NR,2 is connected to the other input of NOR gate NR1, forming a latch. forming cross-connections for The Q output of latch S 1 is connected to the control logic preset input of control logic circuit 16 through inverter I 102 . As explained below, when the power supply is turned on, when a pulse is generated from the P(JR circuit), flip-flop FF1 and latch SR1 reset and hold the counter of control logic circuit 16 to an initial non-counting state. The pulse from the FOR circuit ends and the count of ≦θHz becomes 7 lip-flop FFi.
When the first 1QHz pulse appears at the Q output of flip-flop FF1, latch SR1
properly initializing the control logic circuit 16 to a counting state;
Set to a state that causes a load circuit control sequence to be initiated.

The FOR circuit cooperates with the C-H circuit 18 to generate the voltage Vdd.
When starts increasing from zero, it causes the control logic circuit to start operating. When power is first applied, control logic 16Fi is held in a preset state that inhibits sequential operation. This inhibited state continues until the voltage Vdd exceeds the first high threshold. That is, when the logic circuit in the IC is in the process of becoming a well-defined output state (ie, becoming valid) due to an increase in voltage Vdd from zero.

The output state of the FOR circuit 17 also becomes valid and, together with the C-H circuit 18, sets and holds the control logic circuit 16 in the desired initial state until the first Schmidt threshold is exceeded. Once started, the control sequence is such that when the normal voltage Vdd is reached, the starting sequence ends;
and so on until the control logic enters a static final state.

If the voltage Vdd fails (during the starting sequence or after its completion), the FI (continuously monitoring the voltage Vdd) FOR circuit detects that the voltage Vdd has fallen below a predetermined second value. sense the time. ``If the voltage Vdd falls below a second value, the reset circuit is activated to reset and hold the control logic circuit for a predetermined period of time. When the voltage Vdd rises again, the operation is performed in the same way as when starting the engine.

The operation of the FOR circuit will be explained in more detail with reference to FIGS. 2 and 3. FIG. 2 shows two waveform diagrams useful in understanding the operation of the present invention. To ensure that the logic circuits in an IC design reach a desired initial state and a predetermined minimum power supply voltage for the electronic device to operate reliably.

Assume that after an element of the logic circuit is enabled, it requires a predetermined period of time to continue applying the appropriate preset signal. In this example, the nominal power supply voltage Fi7V (Vdd
), and the individual stages of the logic circuit are assumed to be enabled at approximately /, 5' volts. The entire circuit will not operate reliably at this value, but will operate at about 3 volts. In these conditions, the reset pulse of the FOR circuit, which presets and holds the logic circuit in a predetermined initial state, should be activated once the voltage drops below 3j volts. For this purpose, a voltage fault signal is generated at 3t volts and (when the power is turned on) G2! A hysteresis gate is provided to generate a signal that the voltage is sufficient in volts.

To ensure that there is sufficient time to initialize the entire circuit after the circuit is activated, the designer must use a period of 0 - λθ microseconds measured from turn-on (to). It was decided that it was appropriate. This delay time is achieved in this example by providing a separate low voltage Vdd power supply with a separate filter having a predetermined minimum rise time for the Vdd characteristic. For this rise time, R4 and C4 are selected by conservatively assuming a known (worst-case) current outflow in the IC, and assuming that to corresponds to the peak of the waveform of the main AC line (as the worst-case). It is set by With these assumptions, g7j
The charging time required to reach the first threshold of V is:
! It should be greater than θ microseconds. Instantly power up to 3! A similar test (usually more severe) is performed for temporary drops in the power supply that drop below the dropout threshold, but increase again to the high threshold of 1A7j volts. Also, this time limit is!
θ microseconds should be exceeded. Typical conservative values are θθ2,2 microfarads for element C4 and 622 ohms for element R4.

The upper one of the top pair of waveforms in FIG. 2 is plotted against time starting from turn-on, which activates hysteresis gate S1, and ending during a brief drop in voltage Vdd, which activates gate S1 again. voltage Vd
This is the waveform of d. Connection point 20 (i.e. gate S1
The voltage V20 at the input (to the input) is plotted together with the voltage Vdd for the same event. In this example, the normal operating voltage of voltage Vdd is l/i71. It's a bolt.

The voltage Vdd and the voltage at node 20 can be increased or decreased by 1, and the voltage at node 20 may be the normal operating voltage 6. /volt, which is a voltage that is approximately constant than the voltage Vdd (for example, /,
2 or /Tavolt) low. The next waveform on the bottom is the output of NAND gate NDIOI within hysteresis gate S1. This is logically inverted by inverter 101 and forms the output of hysteresis gate S1, depicted below. Hysteresis gate S
The output of 1 is a pulse, and the amplitude of this pulse is equal to the voltage V
Voltage Vdd available for values θ volts smaller than dd
limited by. When the selected circuit goes into a well-defined state (ie, becomes enabled), which occurs at approximately /Ovolt, the output pulse of gate S1 is initiated. Gate S1 by using a common Vdd power supply
turns on earlier than the circuit under its control, inhibiting counting from that point. Voltage Vdd is ¥7! Assuming that the higher threshold of the hysteresis gate trips when volts is reached, the R4.04 time constant and IC load will provide the shortest time for the crossing of the threshold to terminate the output pulse of gate S1. decide.

FIG. 3 illustrates the factors that set the voltage that terminates the output pulse of gate S1 during power supply turn-on. In a hysteresis gate, the threshold value is dependent on the voltage Vdd and is in fact a substantially constant proportion of the voltage Vdd, with the higher threshold being a substantially constant proportion of the voltage Vdd (eg.

θ3 to θ7jVdd), and the lower threshold is a substantially constant ratio of the voltage Vdd (for example, θ3.!).
? θ, 3-OVdd). The topmost waveform in FIG. 3 shows the voltage Vdd, and is set on a non-linear scale with voltage on the vertical axis and time on the horizontal axis so that the waveform of the voltage Vdd becomes a straight line. The higher threshold of the gate S1 is set at a ratio of 02j according to this proportional relationship. In the embodiment of FIG. 1, the voltage V20 is the voltage Vdd
More almost/! Volt is the lower value and the higher threshold is crossed at time t2, at which time the output pulse of gate S1 ends.

If the voltage at node 20 is two diode drops below voltage Vdd, as in the embodiment of FIG. 9, then the FC threshold will be crossed at time t3 and the pulse will be longer. The first example pulse of gate S1! Given θ microseconds, the pulse in the second example is (other things being equal) /2! It is a microsecond.

The value of voltage Vdd at which the higher threshold occurs is calculated as follows.

■H=θ73 Vdd-Vdd-Vgs.

Here, Vgs is the voltage drop across element T1, and the ratio is θ7! It is assumed that

If you solve this, Vdd... become.

Assuming VgS,=/j volts, the calculated higher threshold is θ volts. in fact.

Mainly due to the fact that said ratio is rather close to θO3, the threshold value is G2! Become a bolt. The lower threshold is similarly approximated with the same result if calculated using a percentage of 0 evenings.

■L: θjVdd-Vdd-V,.

When you solve this.

Vdd=JVg.

become.

Vgs, =/,! volts, the calculated lower threshold would be 3.0 volts.

In fact, the threshold is 3.0 volts.

For proper operation, the resistive FBT element T2
Must have a forward bias to "sink" 1. This connects the gate of element T2 to voltage V
This is done by connecting to dd.

vdS2=■dd−VgS.

Vgs2=Vdd As a result, element T2 has a voltage Vdd of about /,j volts or more
Turn on.

Refer to the graph in FIG. The output pulse of gate S1 turns on latch SRi, which applies a "preset" pulse shown below the output pulse of gate 81 to the control logic. The output pulse of gate S1 opens flip-flop FFl, and the output pulse of 1.20Hz
The clock is supplied to the flip-flop FFi, and the AO for the flip-flop FF1Fi control logic circuit 16 is
Generates a Hz clock. (The two clock waveforms are drawn on a larger time scale than the one at the start, as shown). When the first 60 Hz clock pulse clears flip-flop FF1, the set signal from the Q output of flip-flop FFi is provided to the S output of latch 8Ri. At this time, the output of latch SRi goes into the "F set" state, and the control logic circuit, which had been held in its initial state up to this point, is opened.

If the voltage Vdd drops momentarily, as shown on the right side of the graph in FIG. 3, the hysteresis gate will generate a pulse at time t4 when its output falls below the lower threshold. (In the worst case, if the voltage increases immediately, the gate S1 that has just started at time t4
The reset pulse ends at time t5. The minimum duration (between times t4 and 15) of the reset pulse in this case is set by the difference between these thresholds and the recovery speed of voltage Vdd.
Define the hysteresis requirements of the circuit (the difference between the higher and lower thresholds) and the magnitude of that difference. In this figure, the duration of the pulse is reduced by a factor of approximately 30 in the worst case transient.

If you need a larger value of hysteresis (difference between high and low thresholds), use the ≠ or 5th value.
The illustrated embodiment may be used.

In these embodiments, a hysteresis gate is used as in FIG. 7, but in FIG. μ another diode D1 (or diode-connected FET element T4 in FIG. 5) is used. Additionally, it is connected in series with elements T1 and T2 between the Vdd bus and ground. In both examples, the element DI (T4)
Another PET (T3) is inserted in parallel with , and the gate of this FET is connected to the output of gate S1. FET
When element T3 conducts, it becomes element Di (or T4)
to increase the voltage division ratio at the input of gate S1. As shown in FIG. 3, the higher threshold is increased by the voltage drop across element DI (or T4), and the reset pulse of gate S1, as shown in FIG.
The time between times t1 and t2 is expanded to the time between times t1 and t3 (in the case of the embodiment of FIG. μ).

Vdd-Vgs, -VB=VH The lower threshold is approximately the same as in the first embodiment.

Vdd - Vgs = V L In the embodiment of Figure 1, since the p-type material of device T1 is connected to voltage Vdd, the "body effect" of device T1 causes the duration of the reset pulse of gate S1 to be slightly longer. ing. If desired, one can use an n-channel for element T1 and connect its p-type material to the source to eliminate this effect. As mentioned above, the embodiments of FIGS. Substantially increases the period.

The duration of the output pulse of the microsecond and time gate 481 is a conservative choice for the set and hold functions in this particular application.

In the circuit shown in Figure 1, the time is determined primarily by the requirements of the NOR gate NRi of the flip-flop FFi and latch 5) tl to reach the desired initial state (as the voltage Vdd increases from zero). Since it is set, it can be substantially reduced. The output of the C-0 circuit is 1. of the flip-flop FF1. Since it occurs at the next output of OHZ, the control logic 16 has a few more milliseconds.

This several millisecond period ensures that the control logic 16 is properly preset.

However, since the response time of the circuit is usually fixed for a voltage Vdd of sufficient value, the duration of the output of gate S1 cannot be accurately determined during turn-on from conventional design values. When the voltage Vdd is lower than the normal design value, the delay time is usually quite large, and this uncertainty means that the output pulse of gate S1 is made larger than necessary.

Although a preferred form of power-on reset circuit is shown, other types of series circuits may be used. For example, a FET (T2) with a long channel of high impedance between the Vdd bus and ground
A diode-connected wide channel FET (Tl) connected in series with the hysteresis gate and which forces the output voltage to the hysteresis gate to always be approximately a constant value below the supply voltage (Vddl) sacrifices some performance. However, it may be replaced by a voltage divider network that can apply a voltage less than (and proportional to) voltage Vdd to the hysteresis gate.

Still another power-on-reset circuit is shown in FIG. In FIG. 6, a combinational circuit increasing the hysteresis is provided consisting of diode D2 and switching transistor (T6), which results in a voltage divider at the input to the so-called "gate" circuit with transistor T5! I'm making adjustments. P 01 (The circuit need not have any other means of separating the higher threshold from the lower threshold other than by this combinational circuit.

Furthermore, Fig. 6 shows a P (IR circuit bipolar type).The power supply voltage (Vcc) is the transistor T.
5f: When the point is reached such that the series diode conducts at a current level large enough to forward bias, the output at the gate of transistor T5 goes low. The voltage at which switching occurs depends on the value of resistor R1 (usually high, eg jOK) and typically occurs when voltage Vcc exceeds 2-//l/L volts. P.N.
P Transistor T6 is turned on and the transistor T5 is fully conductive so that the output of the circuit on its collector is at ground potential until the upper diode T2 is shorted and pushes up the first threshold due to the diode drop. It is not possible. When transistors T5 and T6 conduct, a normal operating condition with low output occurs. Voltage V
cc decreases, 1. If you go below Yo Porto, the output will be "high"
become the level. The lowering of the threshold is caused by the diode D2
is effectively excluded from the circuit.

For the power-on reset circuit to be effective, the PAR circuit must provide a reset pulse while the storage element reaches a known valid state. ° This means that when the logic circuit is enabled, the hysteresis gate S1
requires input to be at a low level.

This low level is set by conduction of pull-down element T2 in the TI-T2 series circuit.

Once voltage Vdd exceeds voltage Vtn (threshold voltage of an n-channel device) during power-up, device T2 conducts, pulling node 20 to a low level. Node 2
0 remains low until pulled up by element T1. When the voltage Vdd exceeds the voltage 1Vtpl (threshold voltage of a p-channel device) due to the gate-drain (diode) connection of T1, T1 begins to conduct.

For any level of Vdd > l Vtp l, node 20 is at a voltage level such that the current from element T1 balances the pull-down effect of element T2.

Due to the current capability of element T1, which is thicker than element T2, node 20 tends to track very closely one threshold level below voltage Vdd.

In the region of turn-on, ie at a voltage Vdd close to the voltage I Vtp l, the weak diode effect due to the small current rounds the p-channel threshold somewhat. This is Vgs=Vds
This can be determined by examining the FET characteristics in the case of .
In this way, for a small region close to Vdd = l Vtp l, element T1 does not turn on strongly, so
Has another effective pull-down ability.

Also, as mentioned above, since node 20 is the input to hysteresis gate S1, the voltage at node 20 must be low when gate S1 is enabled.
In the embodiment of FIG. 1, the higher threshold of gate S1 is not well defined for small voltages Vdd. Therefore, this embodiment requires 1*t*tpl>Vtn for proper operation. 1
Vtp+'::Vtn.

For the case, the voltage Vd increasing from the voltage IVtp1
A hysteresis gate with a high threshold value for d that is significantly greater than Vdd/,2 is required. To avoid this complexity, more conventional hysteresis gates can be used in embodiments such as those in FIGS.

In the embodiment of FIGS. ≠ and 5, another series element is added between the Vdd bus and the connection point 20. Initially, the voltage at node 20 is not known until voltage Vdd exceeds voltage Vtn. At this time, the connection point 20 is connected to the element T2
is pulled toward the lower level due to conduction. However, there is no pull-up to node 20 until voltage Vdd is high enough to turn on all elements above node 20. In the case of the embodiment of FIG. and 0.
j-0, plus the reverse gate/body effect due to the 6 volt source-to-substrate voltage). In the embodiment of FIG. 5, the voltage Vdd level is 1
It is the sum of Vtp 1 and the threshold of element T1 (1 Vtp l plus the body effect due to the voltage drop across element T4). Once this voltage Vdd level is reached, the voltage acts as in the embodiment of FIG. That is, the voltage tracks approximately a constant level below voltage Vdd to provide offset/rounding at very small current levels. this is,
When gate S1 is enabled (l Vtp l −Vtn
), ensuring that the input to gate S1 is known and appropriate.

Once gate S1 changes state (and the FOR ends), the added element is removed by element T4.

As a result, these circuits operate in exactly the same manner as the embodiment of FIG. 1 when the supply voltage decreases. The net result of this is that the voltage Vdd level at which the voltage at node 20 begins to rise increases, providing additional hysteresis to the overall function.

The gate S1 shown in FIG. 1 is a special hysteresis gate consisting of a plurality of NAND gates forming a low cost and effective two threshold gate whose threshold is proportional to the voltage Vdd. It is. This is a practical choice, but others may be used. special CMOS
A hysteresis gate (FIG. 1) and a bipolar transistor gate (FIG. 6) are illustrated, but of course, as previously discussed, have inherently low Vdd operating characteristics;
Obviously, other digital threshold circuits may be used to generate digital outputs. In addition to conventional gates and gate circuits, the threshold circuit may include operational amplifiers and comparators.

The circuitry used here to provide the output to the gate at connection point 20 is preferably integrated, non-reactive, and forms a conductive path between the vdd bus and ground. do. The components used herein may include semiconductor devices (including diode-connected devices), semiconductor diodes, and/or resistors that can be formed into ICs.

The FOR circuit ensures that, at power-on, all important functions are contained on the IC in question.
It is useful not only for initializing ICs, but also for initializing ICs that normally receive their signals or inputs from other sources during start-up. This is especially true if, for example, the IC in question receives signals from a microprocessor. Generally, instructions from a microprocessor are not sent out continuously, but
Once sent, it is latched in the IC's instruction register. In the event that the microprocessor fails during turn-on, it is important that the IC be powered up to some known safe default state.

For example, in the case of a motor controlled by an IC, the IC that is the interface to the motor will initially default to the "default state" if the microprocessor fails.
It is important that this is set to 'Off'. Not being able to control a turned-on motor is obviously dangerous, so a FOR circuit can be used to initialize the state of the control logic to ensure a safe condition.

In a preferred embodiment, a low voltage DC power supply for an integrated circuit draws power from a higher voltage DC power supply. This high voltage power supply is designed to power a load circuit that is typically 100 watts at a current of /ampere. A low voltage power supply is only needed to power the integrated circuit, often on the order of 10 milliamps. When a high voltage power supply is started, the 9 hours during which the output voltage rises depends on the phase of the AC waveform at the time it is connected to the DC power supply, the size of the filter capacitor (C1), and the apparent power of the generator. Depends on acceptable internal and load impedances. These rise times are often quite large under worst-case conditions.

Therefore, the desired minimum gradual increase in the voltage Vdd when supplied to the control circuit can be well achieved by the usual amount by using a separate RC power supply, as exemplified herein; In this case, the sizes of both series resistor R4 and filter capacitor C4 can be easily selected to gradually increase the rate of increase of voltage Vdd as desired. The example values of 27 ohms (R4) and 0.022 microseconds (C4) were chosen to optimize other factors, but here the minimum required at T('tSO microseconds) is It was appropriate to give a delay time.

[Brief explanation of drawings]

1 is an electrical circuit diagram of an electrical control device including an integrated circuit with a "power-on-reset" function, using 6MO8 technology; FIG. FIG. 3 is an idealized series of waveform diagrams applied to the power-on reset circuit shown in FIGS. FIG. 5 is two electrical schematics of an alternative power-on reset circuit using the CMO8 configuration fabrication method, and FIG. 6 is an electrical schematic of another power-on reset circuit in bipolar form. 11... Control integrated circuit, 12... Load circuit,
15... Power switching circuit, 16... Control logic circuit, 17-... Power-on reset circuit, 18...
・Clock and POR holding circuit, 19.../20H
z Timing generation circuit, FF1...Flip-flop, sl,... Hysteresis gate, SR1...e
Set/reset latch, TI, T2...FET cumulative element

Claims (1)

[Claims] / An integrated circuit, wherein power of the integrated circuit is supplied by an external power supply, the voltage of the external power supply increases at a predetermined rate after turn-on, and a logic element of the integrated circuit is powered by an external power supply. In electrical control devices that must be set to a predetermined initial state when turned on. A. The integrated circuit (IC) for connecting to the external power supply
) with first and second power terminals on the top. B. the IC including at least seven storage elements connected between the first and second power supply terminals for supplying power and having a terminal for setting the state of the elements;
and a power-on reset (FOR) circuit on the C6 IC. (a) a series circuit that forms a conductive path between the first and second power supply terminals, operates at approximately the same power supply voltage as the memory element built-in circuit, and supplies an intermediate voltage with a voltage lower than the power supply voltage; and (b) a conductive non-reactance path is formed between the first and first power supply terminals, the circuit operates at substantially the same power supply voltage as the memory element built-in circuit, the input is connected to the output of the series circuit, and the output is FOR circuit output. having a relatively high threshold and a relatively low threshold, generating a preset pulse when activated, and generating the pulse when the higher threshold is exceeded; and setting the first threshold in relation to the rate of increase of the voltage to provide sufficient time to terminate the storage element and reset the storage element circuit upon turn-on. A combination comprising a (FOR,) circuit. The lower threshold of the FOR circuit is equal to the power supply voltage above the minimum voltage necessary for reliable operation of the circuit with built-in memory element, and the difference in the threshold voltage is determined by the temporary difference in the power supply voltage. In the event of an interruption,
It is set in relation to the rate of increase of the voltage so as to provide sufficient time to reset the memory element built-in circuit. The combination according to claim 1. 3. The digital threshold circuit of the FOR circuit is 6
It is a hysteresis gate with two thresholds. The combination according to claim 2. The FOR circuit is responsive to the output of the digital threshold circuit to reduce the output voltage of the series circuit in relation to the power supply voltage when a first threshold of the FOR circuit is exceeded. The POR circuit includes a semiconductor switch that causes a difference between the seventh and second threshold voltages of the POR circuit. The combination according to claim 2. j the digital threshold circuit of the FOR circuit is a hysteresis gate with two thresholds; The FOR circuit is responsive to the output of the gate to reduce the output voltage of the series circuit in relation to the power supply voltage when a first threshold of the POR circuit is exceeded;
3. The combination of claim 2, including a semiconductor switch that increases the difference between the first and second threshold openings of the OR circuit. B The smaller voltage in the series circuit is approximately constant. The combination described in claim 1. 7. The combination of claim 1, wherein the digital threshold circuit is a gate, and the threshold of the gate is a substantially constant percentage smaller than the power supply voltage. A combination according to claim 7, wherein the smaller voltage of the series circuit is a value corresponding to the voltage drop of a conducting semiconductor circuit element. 2. The series circuit comprises a first semiconductor circuit element diode-connected to supply a substantially constant voltage corresponding to the smaller voltage, and a second high-impedance semiconductor circuit element. The combination described in Range 2. /θ The gate is a hysteresis gate. The combination according to claim 2. // The external power source is (a) a high-voltage DC power supply; and (b) is supplied with power from the high-voltage DC power supply and is connected to an IC.
low voltage including a filter capacitor and a voltage drop resistor selected to have an output voltage appropriate for operation of the storage element and to ensure that the output voltage increases at a sufficiently low rate to reliably reset the storage element internal circuitry. It consists of a DC power supply. The combination according to claim 2. A combination according to claim 1, wherein the low voltage DC power supply includes a Zener diode connected in parallel to the filter capacitor and having a value appropriate for operation of the IC.