FR2503511A1 - Digital switching system for telephonic auto-commutator - utilises microprocessor in marker unit to drive memory controller for buffer memories in switching network - Google Patents

Abstract

The input connections (32LE) are shared between four amplifying input circuits (CAE1-4) containing amplifiers (AF) and synchronising units (SYN). Each amplifier circuit is connected to a buffer memory (CMT1-4) containing input control circuits (CE) and serial to parallel data converters (CSP). An access circuit (CA) allows access to the buffer memory (MT). A counter (CR) provides downstream control of the addressing while memory read is enabled by a control circuit (CMC) driven by the marker (MQ) containing a microprocessor (mpc). The microprocessor is connected via duplexed point to point connections (RIT) using access units (AR1,2). A clock unit (MD) provides the necessary clock signals from an oscillator circuit. The memory contents are output via an output amplifier circuit (CAS) containing a buffer register (R) and parallel to serial data converter (CPS) which serves a group of output amplifiers (AS).

Description

Device for controlling a digital connection network
The invention relates to a control device for a digital connection network, in particular a distributed control network.

It is applicable in 1-. telecommunications industries, and in particular in the time automatic telephone exchanges.

 It is known to carry out so-called "passive" checks by taking digital samples at various points of the connection network, and "active" checks, that is to say with injection of known samples and taking. An embodiment of such checks in a time switch is described for example in French patent No. 79 25475 of the applicant. It is a PABX controlled by central computers comprising, in the various sub-assemblies, means of selection and access to checkpoints and means of centralizing orders and reports of checks. Such a solution would require prohibitive means in the case of a control center with distributed architecture.

 The object of the invention is to allow control as exhaustive as possible and which requires very few specific means; the invention proposes a much less expensive solution for such a central and using the already existing means as much as possible.

The subject of the invention is a device for controlling a distributed control digital connection network comprising a central network to which are connected, by multiplex links, control units and terminal units each comprising a connection matrix, and the central network being organized in independent switches equipped with markers controlled by the control units, characterized in that it comprises in each switch means for taking samples from the incoming and outgoing multiplex links and injection means d active control code samples and the fact that, for checking the correct establishment of a bidirectional connection path between a requesting terminal and a requested terminal, it comprises in combination the following means - means for looping back the reception and transmission in each of said terminals,
- said means for injecting and taking samples,
means for comparing a sample injected into a switch and the same sample taken at the input of the same switch after the complete journey of the connection path looped through at the terminals.

 According to another characteristic of the invention, the loopback in a terminal is carried out upstream of the filtering and coding circuit, which allows a test, with a precision chosen in advance, of the operation of this circuit.

 According to yet another characteristic of the invention, the control of the connections, relating to a conversation between terminals, is carried out between the off-hook of the requested terminal and the start of the conversation by a succession of messages between control units, terminal units, markers .

The invention will be clarified by the description which follows of a preferred embodiment of the invention, given by way of nonlimiting example, with reference to the appended drawing which represents
- Figure 1, a general diagram of a switch with time connection network,
- Figure 2, a diagram of a subscriber terminal unit,
- Figure 3, a general diagram of a connection network plan,
- Figure 4, a general diagram of a time switch,
- Figure 5 (divided into two parts, Figures 5A and 5B, for format requirements, connected to point S) and Figure 6, a diagram of the main circuits of a switch according to Figure 4.

- Figure 7, a diagram of a marker and an automaton for accessing control links,
- Figure 8, a principle diagram of the control of a path.

 The automatic switch with time connection network represented in a simplified manner in FIG. 1 is made up of three main sets: terminals, connection network, control. It includes - Groups of GuTl to GuTm terminal units comprising subscriber terminals, analog and digital circuits, and auxiliary signaling terminals, transmission of tones and talking films, line test subscribers and circuits, conference circuits, etc.

- A central connection network with a single switching stage, organized into independent plans, for example four plans
RXA to RXD. the figures given here and in the following are simple examples intended to specify an embodiment or to simplify the representation.

 - A distributed architecture control unit formed by groups GUC1 to GUCk of identical UC control units, for example microprocessors. The control units proper UC1 to UCq are standardized. The control assembly also includes units UCP1 to UCPf which manage groups of peripherals PF1 to PFf These units can be identical to the preceding ones, but they are not completely trivialized because of their physical links with the peripherals.

The links which interconnect these three sets are as follows
- The terminal units UT to UTp are linked to each plane
RXA to RXD of the connection network by a multiplex link MX1A to 1XmD of 32 channels of 8 eb, with a speed of 2 M e.bls. The UT units of the same group are connected in parallel to the same MX multiplex links.

- The UC control units (UC1 to UCq) are also
q linked to the connection network by multiplex links MXm + 1A to MXnD, at the rate of one link per GUC group to each plane. The messages exchanged between control units and terminal units use time paths of the MX links, connected by the connection network in a semi-permanent and reconfigurable manner.

Data transmission channels with a speed of 64 k e.b / s are thus produced which are used according to a so-called HDLC procedure defined by the CCITT ISO standard.

- The UC and UCP control units are linked together by a double point-to-point link for safety reasons (RIT1,
RIT2). It is a serial link also using an HDLC procedure. Access to the link is managed by a distributor (DR1,
DR2) which issues emission authorizations and super targets for duration of use. The link comprises five pairs of wires to each connected station ensuring the functions of call, authorization, clock, transmission and reception.

 The links between the control units UC and the terminal units UT are made in the connection network by means of semi-permanent connections established between the channels MIC.

 The central connection network RXA to RXD is controlled by markers MQ1 to MQd controlled by the control units UC also via the links RIT1, RIT2.

 All the units mentioned above (UT, UC, UCP, MQ) have a HDLC type transmission / reception circuit for messages, for example MC 6854 circuits from the company MOTOROLA or 8273 from the company INTEL.

 For UT terminal units, it is also necessary to have a switching stage in each UT unit to allow any terminal to be connected to a time channel of any of the MX multiplex links which serve this unit.

 An example of a subscriber terminal unit is shown in FIG. 2. Each terminal T1 to T p is formed of a line circuit CL, comprising means for supply, protection, loop supervision and ring injection, and an analog / digital filtering and coding FCD circuit (CODEC).

 The terminal unit is controlled by an mP microprocessor connected to the MX multiplex links by an HDLC transmission / reception circuit. The switching stage is in this example an MCX switching matrix of the spatial type.

 The time switch is performed at the CODEC circuits by synchronization on the chosen channel, by a microprocessor control. This also controls the line circuits CL via an IS interface for supervision and control.

 The central connection network is detailed in Figure 3.

It has a single switching stage and is organized into four independent plans. Each connection network plan has a capacity of 128 multiplex links, i.e. it can connect any channel from one of the 128 incoming LE links to any channel from one of the 128 outgoing LS links. .

 A connection network plan includes four switches CX1 to CX4, each equipped with a marker MQ1 to MQ4, and with a capacity of 128 LE incoming links and 32 LS outgoing links. The incoming LE connections are therefore multiplied on the four switches of the plane.

 The structure of a switch CX is shown in FIG. 4. The 128 lines LE are distributed over four input amplification circuits CAE each comprising 32 amplifiers AE and a synchronization circuit SYN. CAE circuits are common to all four switches in the same plane. Each circuit CAE is connected to a buffer memory circuit (CMT1 to CMT4) successively comprising an input control circuit by sampling CE, a series-parallel conversion circuit CSP, and an access circuit CA to a buffer memory MT . The access circuit also allows the injection of samples for a so-called "active" control of the connection network.

 The MT memory contains 1024 words of 8 e.b. (1 word per channel of the 32 LE lines concerned), and the input-output bit rate of the memory is 8 MHz, that is to say a bit rate close to the maximum allowed with the TTL technologist used.

 The addressing is of the "downstream command" type, that is to say it is supplied in writing by a counter CR and in reading by a command memory circuit (CMC) controlled by the marker MQ. The control memory provides the read address of each of the four MT memories. It is itself addressed cyclically in reading and by the writing marker to allow the recording of each new connection or disconnection.

 The marker MQ comprises an microprocessor mPC which is connected to the links RIT1, RIT2 by access circuits AR1, AR2 described below.

 The outputs of the four buffer memories MT1 to MT4 are connected in parallel to an output amplification circuit CAS comprising buffer registers R, a parallel encoder - CPS series, an output sampling circuit CS and a group of 32 AS amplifiers connected each to an LS line.

The set of clock signals HR1 to HRq necessary for the operation of the switch is supplied by a signal distribution module MD controlled by oscillators 01 to Od
The connection network is modular: up to 32 G groups (GUT or GUC) it is sufficient to equip a switch with a single CMT buffer memory circuit.

 From 33 to 64 groups, two switches are required, each equipped with two buffer memories.

 From 65 to 96 groups: three switches each with three buffer memories.

 From 97 to 128 groups: four fully equipped switches.

 The following description relates to an embodiment of the main circuits constituting the switches.

 The switching circuits CMT and CAS are shown respectively in FIGS. 5A and 5B. The clock and synchronization signals are distributed by a time base circuit BT1 which is itself synchronized with the distribution module MD of the switch (FIG. 4). The circuit BT1 delivers signals h which will not be described in detail since they are in the field of the known art, and they arise from the operation of the circuits, as described below.

 The sampling ce on the links LE is carried out by means of a multiplexer MX1 and the address of the link to be checked (ACE) is supplied by the circuit CMC.

 The CSP conversion circuit is formed by four integrated circuits 1, 2, 3, 4 called "MICSPA" with a capacity of 8 links each. The outputs of the MICSPA circuits are connected to four registers R1 to R4. The routing of the samples to the tempon memory is carried out by a multiplexer MX2, one input of which is assigned to the injection of the active control code ca marked for example by wiring.

 "AND" P gates validated by the time base control the entry of the registers of the CSP circuit, of the memory and in general of all transfers. These doors will no longer be mentioned later, so as not to add to the description.

 To allow the memory to be used at maximum speed, it has been split into two parts M1 and M2 used simultaneously, one for reading and the other for writing. The read address AL supplied by the control memory is routed by a register R5 and multiplexers MX3 and MX4. The write addressing, supplied by a counter CBî with a rotation frequency of 8 MHz, is routed by a register R6 and the same multiplexers. The counter has a doubled capacity (11 e.b. instead of 10 to address 1024 Words) to allow the alternating use of the two memories: the e.b. of low weight directly controls the multiplexer MX3 and the input of the memory M1, and through an inverter I1 the circuits MX4 and M2. The counter CB1 is synchronized by the circuit BT1 (loading at a K / wired value).

 The memory outputs are routed to the parallel output S (8 eb) of the CMT circuit by registers R7, R8 and a multiplexer MX5 addressed by the least significant part of the counter CB1, and controlled by a flip-flop B1 which receives the validation signal Vk access to the CAS output circuit. The signal (K = 1 to 4) is delivered by the CMC circuit and makes it possible to select the buffer memory which must supply the sample conveyed at this instant by the switch.

 For the injection of the active control Ca, the incoming link address ACE supplied by the circuit CMC is compared with the 5 e.b. most significant of the counter CB1 (comparator CP1). The address register Rg of the multiplexer MX2 comprises 3 e.b. : two supplied by the most significant of the counter CB1 and one supplied by an "AND" gate PE which receives the output of the comparator CP1, an injection top ti supplied by the circuit CMC in synchronization with the channel concerned, and a signal of validation of circuit Vck (k = 1 to 4).

 At the input of the CAS circuit, a multiplexer MX6 makes it possible to receive either the output S of the four circuits CMT of the switch, or a wired idle code RE which is systematically transmitted on the connections LS which are not connected. The command to inject this code (cre) sent by the CMC circuit is transmitted by synchronization flip-flops (B2, B3) to the address input of the multiplexer MX6.

 At the output of the multiplexer MX6, the samples are distributed successively to four registers R11 to R14 under the control of a shift register with four positions R10 receiving pulses at the frequency of 8 MHz and synchronized with the outgoing links LS.

Samples finally pass through intermediate registers
R15 to R19, the CSP conversion circuit formed by four MICSPA circuits (these circuits are capable of performing parallel / serial and serial / parallel conversions), and four output buffer registers R19 to R22.

 The input of the MICSPA circuits is validated by a flip-flop B4 activated in synchronization with each outgoing time channel.

 The cs output control sampling is carried out by a multiplexer MX7 whose address (AC5 = 5 e.b.) is provided by the CMC circuit.

 The control circuit CMC represented in FIG. 6 essentially comprises a control memory MC with a buffer register RT for addressing the buffer memories, passive (active) (active) (bd) control circuits, and registers of input and output connected to the BD data bus of the marker mPC microprocessor (RE1 to RE5, RS1 to RS3). These circuits are controlled by a time base circuit BT2 synchronized with the signal distribution module MD of the switch CX.

 The validation signals for transfers between the registers and the BD bus are provided by decoding of 3 e.b. of the addressing bus BA of the microprocessor (decoder DEC2, signals v1 to v5) and by the write command wires Ec and read Lec of the command bus.

 The control memory MC has 1024 words of 13 e.b.

allowing the control of the 32 x 32 channels carried by the 32 LS links: 10 e.b. are used for the address AL of the buffer memories, two for the validation of a CMT circuit (Vk, decoder DEC7) and an e.b. for the command to inject the Cre rest code.

 The description which follows specifies the functions performed on the order of the microprocessor, and the principle of realization of the circuits.

- Write MC memory
a) loading of the register RE1 (commands v1 and Ec),
b) loading of the register RE2 which contains the address of the word to be written (commands v2 and Ec),
c) writing: the memory is addressed by the counter CB2, and a comparator CP2 activates a flip-flop B6 which authorizes writing when the counter reaches the value entered in the register RE2.

- Reading of the MC memory by the marker allowing the CMC circuit test (by comparison with an image of the MC memory written in the marker memory)
a) loading of the address (v2 and EC),
b) reading memory and loading the register RS1, validated by the comparator CP2 and a flip-flop B7,
c) transfer of the content of the RS1 register to the BD bus (v1 and
Lec)
- Input sample loading of an address of 12 eb in the RE5 register (commands V5 and EC), 2 2 eb send a multiplexer MX8 receiving the samples from the CMT circuits (Ce1 to Ce4), 5 5 eb supply the 'ACE address (LE link NO),
. 5 channel address eb: synchronization on the channel to be checked is carried out in the PRE circuit by comparison (comparator CP3) of the address with the content of a counter CB3 synchronized by the time base. The sample is loaded at the rate of the LE link (2 MHz) into an RD1 shift register. The transfer to the RS3 output register is controlled by a flip-flop B8 activated at the end of the sample.

 - Output sampling: identical principle, using registers RE4 and RS2 and a PRS circuit similar to PRE.

- Active control
loading of RE5 register,
the circuit validation signal VCk is supplied by decoding (decoder DEC3) of the two circuit address CMT eb,
loading of register RE3. This register is a command register which provides the command to inject ica of the Ca code, commands for validation, read and write memory (flip-flops
B6, B7) and reset commands.

 a flip-flop B5 validated at the output of the comparator CP3 delivers the top ti when the signal ica is activated.

RIT point-to-point link marker and access (Figure 7)
The MQ marker includes an mPC microprocessor; for example a circuit 8086 associated with a clock circuit 8284 manufactured by the company INTEL. The internal bus B supplies the address bus BA by an address register RAD, and the data bus BD through a bidirectional interface IN controlled by the microprocessor mPC (directional signal s coming from the output DT / R of the microprocessor mPC , and input-output addresses received by an "OR" gate and a DEC4 decoder).

 The marker mPC comprises a program memory MP, for example of the "reprom" type and a random access memory of data MV.

The RIT link access unit includes an HDLC procedure exchange management circuit, an AU control automaton, and intermediate MEM and reception buffer memories.
MRE.

 The HDLC circuit is, for example, of type 6854 manufactured by the company MOTOROLA.

 The automaton AU is formed in a known manner by a read-only logic associated with an address register which receives the input information and with an output register, the two registers being controlled by a clock (input E coming from the OSC output of the mPC microprocessor and which also controls the HDLC circuit). At the input of the access device, the bus BD is validated by an access door PA controlled by an address bj coming from the decoder DEC4.

The accesses are analogous to those which have been described for the CMC control memory circuit.
- Use of the WR and RD commands (son Ec and Lec) of the mPC microprocessor, and of a selection signal (v6 to v10) obtained by decoding (DEC5) of address.

 - Multiplexed addressing of memories MEM and MRE (addressing by the microprocessor by the bus BA, addressing by the automaton AU by counters CB, CB5, according to the operation described below, multiplexers MX9 and MX1o).

- Use of the following additional circuits
incoming data register (RDE) connected between gate PA and bus BH of the HDLC circuit,
outgoing data register (RDS) between the BH and BD buses,
. input buffer register R23 of the memory MRE,
. command register RC containing reset commands RZ and commands of the internal registers of the HDLC circuit (input
A corresponding to the R / W, RSo, RS1 commands of circuit 6854 MOTOROLA) supplied via a multiplexer MX1l controlled by the AU controller (output a). The HDLC circuit can thus be controlled either by the microprocessor , either by the automaton,
call registers RA1, RA2: to access the link
RIT, the microprocessor loads the register RA1, and the clock HR of the link RIT transfers the information in the register RA2 and marks the wire DE. The authorization to send back AE is received by the automaton AU,
A5 station address recognition circuit: this address which is used to identify the stations or machines connected to the RIT links, is wired in this circuit. It is compared, on reception, with the internal address in messages. In transmission, it is integrated into the message,
a programmable PIC circuit for managing microprocessor interruptions makes it possible to take into account the service requests of the PLC in transmission and in reception. One uses for example the circuit 8259 manufactured by the company INTEL. In transmission, the ITE interrupt is supplied directly by the HDLC circuit (RTS output) and a flip-flop B9. On reception, the ITR interrupt signal is supplied by the AU controller which activates a flip-flop B10. These flip-flops are reset to zero by the microprocessor (signal RZ given by the register RC).

The operation of the circuits is as follows
- Request for transmission by the mPC microprocessor
loading of the memory MEM by the microprocessor: the memory MP can contain a complete message of n bytes. The address of the last byte is loaded into the counter CBq,
. the memory is read by the IIDLC circuit under the control of the PLC.

- The counter is activated in declining mode under the control of the signal "ready to transmit eg supplied by the HDLC circuit, indicating that its emission register is empty (TDSR output)
- Access to the BH bus at the memory output is validated by the PLC (output a and A providing a code X for command to write the transmission register of the HDLC circuit).

 - When the counter has returned to zero, an FM message end decoder warns the controller, and the latter controls the HDLC circuit for the transmission of message end codes.

- Receiving messages on the RIT link
The detection of the start of a message marks the FD output of the HDLC circuit and warns the PLC, the latter orders the reading of the reception register of the HDLC circuit, and the AS circuit recognizes the station address.

 For each byte received the HDLC circuit activates its RDSR output (signal pr "ready to receive"). The signal pr validates the clock input of the counter CB5. The PLC controls the reading of the reception register and the writing of the memory MRE (signal X1).

 The controller uses the mPC microprocessor by interruption (ITR). Several messages can be queued in the MRE memory.

The microprocessor comes to read the counter CB and each of the
5 messages contained in the memory.

 Each message gives rise in return to an acknowledgment message.

- Functions performed by the marker
The marker executes the orders supplied by the control unit UC to which it is assigned. Certain orders give rise to a report message.

Connection functions
These functions give rise to the establishment of a one-way connection, that is to say between a channel of an LE input and a channel of an LS output. Each connection can be associated with three kinds of control
- active connection control (eb C of the message),
- LS link rest test before connection (eb R).

- conformity test of the pre-existing connection (eb T)
The information part of the message has 7 bytes
- 1 byte of function 0 0 0 0 1 TRC,
- 3 addresses of 2 bytes (input address, output address, old input address for conformity test).

Disconnections
- Simple disconnection, with or without conformity test,
- Global disconnection of several channels from the same outgoing LS link.

The message has 6 bytes
- function code (1 byte),
- address of the LS link concerned (1 byte),
- 32 eb each assigned to one of the 32 channels, indicating the channels to be disconnected.

Controls
- active control,
- passive control,
- checking by re-reading a connection in the MC command memory.

 The means described allow complete control of the links established across the network, for example conversation paths from the terminal of the requestor to that of the called party.

 The solution adopted for this control, in this application of the invention, consists in injecting the active control code at the level of a marker, and in collecting this code at the entry of this marker after a route using the conversation paths. round trip and the two terminals (Figure 8).

For this it is necessary to loop the incoming and outgoing channels in the terminals, for example upstream of the connection network or upstream of the codec. The latter solution has the advantage of simultaneously allowing a functional check of the CODEC.

We will describe the exchange of messages during this control under the following conditions
- the check is made when the request is picked up,
the requesting terminal unit UT1 and the calling party terminal unit UT2 are managed by separate control units UC1, UC2,
- the switch CX1 which establishes the path in the direction UT2 to UT1 is the same as that which established the connection between the auxiliary terminal unit UTA which provides the call return to the caller, and the unit UT1,
- the switch CX2, which establishes the path in the direction UT to UT2, is in the same plane as CX1,
- the choice and the establishment of the path are carried out by dialogue between the units UC1 and UC2, which respectively control the markers MQ1 and MQ2 of the switches.

Actions and messages
Before the called party picks up, it receives the ringtone and the caller, connected to UTA, receives the RA call return

- when off-hook, UT2 cuts the bell and warns UC2,
- UC2 warns UC1,
- UC1 commands UT1 to loop BL1 from the requester's terminal T1
- UC1 commands MQ1 to replace the LEA - LS1 connection with the LE1 - LS1 connection with active control,
- UC2 commands UT2 to loop BL2 to the terminal of called party T2,
- UC2 commands MQ2 to establish the LE2 - LE2 connection,
- MQ1 performs the active control with direct debit from the LE1 input and reports to UC1.

 Then the terminals are unbuckled, and UC1 makes the transition to the conversation phase with triggering of charging.

 The control by comparison of the codes emitted AC and received can be done with a determined tolerance, for example without taking into account the e.b. of low weight.

We will now describe by way of example the progress of a local communication by following the different phases preselection, numbering and translation in the case of a dial subscriber and a keyboard subscriber, local selection, end of selection, connection with established path control and release. It is assumed that the called party is free, that the calling party hangs up first, and that the calling and called party terminals are managed by different control units UC1 and UC2. Clues 1 are given to the bodies concerned by the applicant and indices 2 to those concerned by the called party
A - Preselection, numbering and translation in the case of a rotary subscriber
Phase 1 - the processor of the terminal unit UT1 cyclically explores its terminals and detects a dropout,
Phase 2 - the unit UT1 notifies the control unit UC1 and indicates to it the number NT of the terminal T1 of the calling subscriber,
Phase 3 - the control unit UC1 searches for a channel V1 between the terminal T1 and the connection network RX and an access channel V1A to the unit for transmitting terminals LUTTONS
Phase 4 - the control unit UC1 warns the corresponding marker MQî of the connection network by indicating to it the channels to be connected,
Phase 5 - the control unit UC1 notifies the terminal unit UT1 that the connection from terminal T1 to the terminal unit UTTON is in progress,
Phase 6 - the terminal unit UT 1 locally connects the terminal T1 to channel V1 of an RXA plan of the connection network,
Phase 7 - the caller's terminal T1 receives the invitation to dial IA from the UTTON unit.

Phase 8 - the terminal T1 sends the first digit CH1 to the unit UT1,
Phase 9 - upon receipt of the first pulse the unit UT1 cuts the connection from terminal T1 to channel V1 to remove the tone,
Phase 10 - the unit UT1 receives, identifies and transmits each digit CH2 to CHn to the unit UC1
Phase 11 - after receiving two digits the UC1 unit performs a first translation for pre-analysis of routing
Phase 12 - full translation after receipt of the expected number of digits, determined by the pre-analysis. At this phase, depending on the type of central and the nature of the call, the control unit UC1 can call a centralized translation service located on another control unit.

B - Preselection, numbering and translation in the case of a keyboard subscriber in multi-frequency code; this case also involves a unit for receiving receivers for dialing in keyboard code UTAUX and a marker MQAUX for the switch which connects the units UT1 and UTAUX for dialing by means of a loop with two different channels and two switches CX1 and CXAUX located in the same plane of the connection network.

Phases 1 and 2 - are identical to phases 1 and 2 of the previous case,
Phase 3 - the UC1 unit searches for a V1 channel to UT1 and a VAUX channel to an available dialing receiver.

Phase 4 - orders to markers MQ1 and MQAUX to establish two-way connections between the units UT1 and UTAUX
Phase 5 - the control unit UC1 warns UT1 that a dialing receiver is connected,
Phases 6 and 7 are identical to phases 6 and 7 of the previous case (the tone is emitted by UTAUX)
Phase 8 - terminal T1 sends the first digit to the UT AUX unit
Phase 9 - the UTAUX unit cuts the dial tone IA
Phases 10 - 11 and 12 - are identical to phases 10, 11 and 12 of the previous case
Phase 13 the control unit UC1 sends a release order to the unit UTAUX
Phase 14 - the control unit UC1 orders MQAUX to disconnect the channel to UTAUX
Phase 15 - the control unit UC1 orders UT1 to disconnect the terminal locally
C - Local selection
Phase 1 - Call of the control unit UC2, which manages the terminal of the called party T2, by the control unit UC1 indicating the plan RXA of the connection network used, the channel V1 which connects the requester and the number NT2 of the terminal T2 requested.

Phase 2 - the UC2 control unit searches for the state of the free, busy, transferred or other called party. If it is free, the unit searches for a channel V2 to terminal T2 in the connection network plan -Phase 3 - it is assumed that terminal T2 is free but that there is no channel in the plan RXA (for example because the corresponding MIC is out of service) the UC2 unit responds to the UC1 unit
Phase 4 - the control unit UC1 searches for a channel V1 in another RXB plane of the connection network
Phase 5 - the control unit UC1 warns the unit UC2 of the plan and channel number to use - Phase 6 - channel search by the unit UC2
Phase 7 - order from the UC2 unit to the UT2 terminal terminal T2 unit, and T2 bell
Phase 8 - response to phase 5 from UC2 to UC1: end of selection
D - End of selection
Phases 1 and 2 - end of selection the UC1 control unit proceeds
- 1: when saving information concerning the communication (message to a backup machine),
- 2: looking for a VRA channel for connection of a tone unit (UTTON) to the unit UT1 for connection of the call return signal to the caller
Phase 3 - order the UC1 unit to the MQ1 marker to connect the V1 and VRA channels
Phase 4 - order from control unit UC1 to UT1 to locally connect T1 to channel V1
Phase 5 - off-hooking of T2 signaled by UT2 to UC2 then to UC1 and stopping of the ringing of the called party
E - Connection with established path control
Phase 1 - order from the control unit UC2 to the terminal unit UT2 for looping through the CODEC of terminal T2
Phase 2 - MQ2 marker order to connect channel V2 (link
LF2 - LS2 to test the connection (figure 8)
Phase 3 - order from the control unit UC1 to the looping unit UT1 of the terminal terminal CODEC
Phase 4 - order from the control unit UC1 to the connection marker MQ1 with test
Phase 5 - test report from MQ1 to UC1
Phase 6 - order by UC1 and UC2 to unwind the CODECs
Phase 7 - establishment by UC1 of the charging and start of the conversation
F - Release
Phase 1 - hanging up of the caller detected by exploration by the UT1 unit then the UC1 unit
Phase 2 - the UC1 control unit issues the tax and alerts the machine that manages the backup - Phase 3 - the UC1 control unit requests the UC2 control unit to release the part of the chain that concerns it
Phase 4 - release order from UC1 to UT1 (local disconnection of T1)
Phase 5 - UC1 order to cut the connection (RXB, V'1, V'2)
Phase 6 - the UC2 control unit searches for a VOCC channel to connect the T2 terminal to a UTTON unit which transmits the busy signal
Phase 7 - order from the UC2 unit to the MQ2 marker to connect V'2 to
VOCC
Phases 8 and 9 - the terminal receives the busy tone and hangs up
Phase 10 - order from UC2 to UT2 to release T2 (local disconnection)
Phase 11 - order from UC2 to MQ2 to disconnect the V'2 -VOCC link

Claims (5)

CLAIMS 1 / Device for controlling a digital connection network for a distributed control branch exchange comprising a central network to which are connected by multiplex links control units and terminal units each comprising a connection matrix and the central network being organized into independent switches fitted with markers controlled by the control units, characterized in that it comprises, in each switch (CX) means for taking samples (MX, PRE, PRS) on the incoming multiplex links (LE ) and outgoing (LS) and means for injecting samples (CP1) of active control code (ca) and by the fact that, for checking the correct establishment of a bidirectional connection path between a requesting terminal ( T1) and a requested terminal (T2), it comprises in association the following means - said means for sampling and injection (MX, PRE, PRS, CP1), - means for looping (bd1, BL2) of the routes d e reception and transmission in each of said terminals (T1, T2), - means for comparing a sample injected into a switch (CX1) and the same sample taken at the input of the same switch (CX1) after the journey complete connection path terminated at the terminals. 2 / control device according to claim 1, wherein said multiplex links are synchronized, characterized in that said sampling means comprise multiplexers (MX1> MX7) connected respectively to incoming (LE) and outgoing (LS) multiplex links, of which the address (ACE, ACS) is supplied by the marker (MQ), and sampling control circuits (PRE, PRS) synchronized by comparison between the time channel number supplied by the marker and the content of a synchronized counter with said multiplex links. 3 / control device according to claim 2, wherein the incoming multiplex links are connected to a switching buffer memory (M1, M2) through a serial / parallel converter (CSP) and a multiplexer (MX2), characterized by the fact that the control code (ca) is injected on an input of said multiplexer (MX2) and that the synchronization of the injection with the time channel is carried out by said sampling circuit (PRE). 4 / control device according to claim 1, wherein a subscriber terminal comprises a line circuit (CL) and a filtering and coding circuit (FCD) characterized in that the loopback (BL1, BL2) of a terminal is made upstream of the filtering and coding circuit (FCD). 5 / control device according to claim 1, wherein the terminal units are organized into groups (GUT) each assigned to a control unit which manages the group and the links which connect it to the central connection network, the establishment of '' a communication between two terminals (T1, T2) being carried out by dialogue between the terminal units (UT1, UT2), the control units (UC1, UC2) which manage these terminal units and the markers (MQ1, MQ2) switches (CX1, CX2) chosen by the control units for establishing the conversation links between the two terminals, characterized in that the looping of the links and the test are carried out by message exchange on links between a first control unit (UC1) and the requesting terminal unit (UT1), between said first control unit (UC1) and a marker (MQ1) of a first switch (CX1), between a second control unit (UC2 ) and the demand terminal unit é (UT2), between said second control unit (UC2) and a marker (MQ2) of a second switch (CX2) and between said control units (UC1, UC2).