FR2484682A1 - Speech synthesiser controlled by programmed microprocessor - uses IC modules for data stores and speech signal - Google Patents

Abstract

The synthesiser receives input signals from an external control device and has two memories for permanent storage of a first set of coded data and temporary storage of a second set of coded data and temporary storage of a second set of coded data, provided by the external control device, respectively. A synthesis processor converts the coded data into digital speech signals, subsequently converted into an analogue speech signal. A selection device responds to a control signal supplied by the control device, to determine which set of coded data is supplied to the synthesis processor. Pref. the coded data comprises reflection coeffts. for controlling digital filters within the synthesis processor, while the memories comprise a fixed value memory and a buffer register respectively.

Description

 The present invention relates to speech synthesizers and relates more particularly to a speech synthesizer that can be realized in inexpensive integrated circuits.

 Speech synthesizers are known in the prior art. U.S. Patent Nos. 3,803,358 and 4,092,495 and US Patent Application No. 901,393, filed April 28, 1978 in the name of the Applicant, describe exemplary synthesizers of US Pat. already known word.

 The invention therefore relates to a speech synthesizer using several integrated circuits for its realization.

These integrated circuits include a speech synthesizer and permanent memory processor, which will be described in detail later.

 The present speech synthesizer is described in conjunction with a consumer-type calculator, but it is understood that many applications in which a verbal response of information or instruction is desired may incorporate this synthesizer.

Preferably, the synthesizer according to the invention is made according to the usual techniques of deep integration, with field effect transistors, for example P-channel metal oxide semiconductor (MOS). preferable that the speech synthesizer is compatible with control circuits such as those that exist in different electronic devices,
An object of the invention is therefore to provide a speech synthesizer with integrated circuits, high integration and low price.

 Another object of the invention is to provide a speech synthesizer electrically compatible with the logic levels of existing transistor transistor (TTL) circuits.

Another object of the invention is to realize
a speech synthesizer using coded speech parameters stored in a semiconductor memory.

 Finally, another object of the invention is to provide a speech synthesizer that can use coded speech parameters introduced by a control device.

 These results are obtained in the manner that will now be described. A speech synthesizer is controlled by an appropriately programmed microprocessor, preferably the central processing unit of a commercial calculator or of the general public type. The speech synthesizer implements data coding and compression techniques to minimize the data rates that are required. coded speech parameters are used to control the reflection characteristics of a digital filter in the speech synthesizer. The output signal of the digital filter is applied to a digital-to-analog converter that converts the digital output of the filter into an audible signal. The reconstructed audible signal can then be used at the input of a current amplifier, with a loudspeaker.

 Other features and advantages of the invention will become apparent from the following description.

In the accompanying drawings, given solely by way of non-limiting example
Figs. la, lb and lc are speech views, alone and connected to a consumer-type calculator
Fig. 2 is a simplified diagram of the essential elements constituting the speech module,
Fig. 3 is a logic diagram of the input / output circuits of the speech module,
Figs. 4a and 4b, placed side by side, form a composite diagram of the speech synthesizer processor,
Fig. 5 is a timing chart of different timing signals used in the synthesizer,
Fig. 6 is a table illustrating the principle of data compression to reduce the data rate required for the synthesizer,
Figs. 7a to 7d form a composite logic diagram of the sync circuits of the synthesizer,
Figs. 8a to 8m form a composite logic diagram of the logic circuits interface between the permanent memory and the central processing unit of the synthesizer,
Figs. 9a to 9d form a composite logic diagram of the interpolation logic circuits,
Figs. 10a to 10c form a composite logic diagram of the matrix multiplier,
Figs. 11a to iid form a composite logic diagram of the scale filter of the speech synthesizer and the excitation generator,
Figs. 12a and 12b are diagrams of the direct access memory of parameters,
Figs. 13a to 13c are diagrams of the parameter permanent memory, and
Figs. 14a and 14b form a composite diagram of the permanent memory of oscillations.

 FIGS. la and lb are perspective views of speech, of a type made according to the invention. The speech module comprises a housing in which the electronic circuits are housed. preferably in integrated circuits (not shown in this figure). An access slot 2 is also provided in which additional memory units may be placed to supplement the initial memory circuits. These circuits are connected by a connector-3 to a commercial calculator, a child's electronic toy, or any device in which a verbal response instruction or information is desired. However, it is understood that other means of connection may be used if desired. 1c represents an embodiment in which the speech module is connected by the connector 3 to a computer 4, with a loudspeaker 5. FIG. 2 represents the essential elements of the synthesizer, including certain elements in the computer, namely the central processing unit 19, the sound amplifier 20 and the speaker 3 which are necessary to use the speech module.

 After describing the external appearance of the speech module, the modes in which it can operate will first be explained, then the general diagrams and detailed masks of the various electronic circuits forming the speech module of FIGS. la and lb will be described.

 In this embodiment, the speech module can operate in two modes which will be explained below.

However, it is obvious that these modes of operation can be modified, or that their number can be increased or reduced. As an example, this module is designed to operate in the following modes.

 In the first mode, the speech mode, the module uses coded speech parameters that reside in a module's permanent sentence memory. The encoded parameters are introduced into the speech synthetic processor chip in which they are decoded and used to reconstruct a time-varying pattern of the speech signal. This model is used to produce a synthetic speech signal.

 In the second mode of operation, the external speech mode, the coded speech parameters are produced by an external source, preferably the central processing unit of a commercial computer. the encoded speech parameters are inputted into the processor chip of the speech synthesizer in which they are decoded and used to produce the synthetic speech.

 Fig. 2 is a simplified diagram of the essential elements constituting the present embodiment of the speech synthesizer. the electronic circuits of this module can be divided into three essential functional groups, one being the speech synthesizer processor 10, another being the command input / output box 11 and the last being constituted by permanent memories 12a and 12b. In the present embodiment, these main functional groups are each integrated on a separate integrated circuit chip, except for the fact that the permanent memories 12 which are integrated on two pellets. The speech parameters coded for the desired speech outputs are stored in the group of permanent memories. Further, other coded speech parameters may be stored in separate dictionary modules, which may be connected to the speech module in a manner similar to that described in United States Patent Application. 003 449 filed January 15, 1979 in the name of the Applicant These other permanent memories are shown in dashed lines, because they can be plugged into the module by the operator, rather than normally housed in the device.

 The processor 10 is interconnected with the memory by a data circuit 15 and is connected to the input / output bus line 18 by the data circuit 16 and the control input / output circuit bolt 11. In one embodiment, coded speech parameter addresses are transmitted by a central processing unit of a commercial computer to the permanent memories 12a and 12b as a processor 10 as shown later. The latter is preferably equipped with buffers capable of addressing several permanent memories. Of course, a central processing unit with buffers of appropriate capacity could issue addresses to several permanent memories and, therefore, in other embodiments, it might be desirable to also connect the input of the unit. processing center directly to the permanent memories.

 The speech synthesizer processor 10 synthesizes human speech or other sounds based on data frames stored in the permanent memories 12a and 12b or 13a and 13b. The processor uses a parameter interpolator of the type described in US Patent Application No. 901,394 filed April 28, 1978 in the name of the Applicant. Processor 10 also uses a digital filter of the type described in US Pat. U.S. Patent Application No. 905,328, filed May 12, 1978 in the name of Applicant O The following description of the speech module assumes a basic knowledge of the operation of the parameter interpolator and the digital filter described in the aforementioned patent applications; it is therefore desirable to read these requests before proceeding to the detailed description of this module. The speech synthesizer processor 10 also includes a digital-to-analog converter which converts the digital output of the filter into analog signals capable of driving a sound amplifier and a speaker. The processor 10 also includes data synchronization, control, storage and compression circuits which will be described in detail later.

Fig. 3 represents the control input / output circuit. This circuit includes NON-ST gates 31, 32 and 33 with three inputs, with open collectors. These logic gates may be similar to those of the SN74LSiO pellet manufactured by vexas Instruments Incorporated,
Dallas, vexas. Two of the inputs of the NAND gate 31 are connected to the voltage Vss. The third input receives an address bit (ADD15) from the central processing unit. Since two of the inputs are always high, the NAND gate 31 behaves as an inverter and its output delivers the ADD15 signal. The door
NAND 32 receives at its inputs the signal SADD15 coming from the output of the NAND gate 31, the speech block authorization signal SBE and the address bit 5 (ADD5). Therefore, the output of the NAND gate 32 is a function of SBE, ADD5 and ADD15. This output is designated WS, write selection, and is connected to the speech synthesizer processor 10. A write selection command from the central processing unit allows the speech module to receive eight data bits over the bidirectional data bus line 17. The NAND gate 33 receives at its inputs the signal ADD15 from the output of the NOR gate 31, the speech block enable signal SBE and the ADD5 signal from the output of the NAND gate 32. Therefore, the output of the NAND gate 33 is function signals
SBE, ADD5 and Ad15. This output is designated RS, read select, and is connected to the speech synthesizer processor 10. A read selection command from the central processing unit enables the speech module to transmit eight data units over the data bus line 17 or commands the module to generate certain status signals in them. pre-determined points along the bus line 17.

 In addition, the processor may emit an interruption signal INT which indicates to the central processing unit a change of state of the processor, which may lead to examination by the central processing unit. the particular state changes which can produce the transmission of the interrupt signal INT will be explained later.

Gate 34 reverses the DISP availability signal at its input to produce the DISP signal to 11 CPU. When the availability signal DISP is high, the central processing unit is locked on the synthesizer 10.

 Figs. 4a and 4b together form a diagram of the processor 10 of the speech synthesizer. The processor 10 has six main functional elements which, all but one, are shown in more detail in FIGS. 4a and 4b.

These six essential elements are the synchronization logic circuit 20, the logic circuit 21 interface between permanent memory. and central processing unit, logic circuit 22 for loading, storing and decoding parameters, parameter interpolator 23, filter and excitation generator 24 and section 25 for digital-to-analog conversion and output. All these essential elements will be described in more detail with reference to FIGS. 15 to 14.

 Figs. 4a and 4b show that the interface logic circuit 21 connects the synthesizer 10 to the permanent memories 12a and Z; Ytfainai to the central processing unit, not shown. The bidirectional eight-bit data line 17 (DO-D7) is connected in the present embodiment to the central processing unit and to the inputs of a buffer 2215 at first in, first out, while the address pins 1-8 (ADD1-ADD8) and instruction 0-1 (IO-II) are connected to the permanent memories 12a and 12b, as well as to the permanent memories 13a and 13b if they are used. interface 21 transmits address information from the central processing unit to the permanent stores 12a and 12b, via the address register 213, - on the address pins 1 to 8. A register control 210 stores a three-bit command from the central processing unit, which is decoded by a control decoder 211.The latter responds to six commands: SPE, or speech, for the synthesizer to access data from of permanent memory and speaks in response to these data es; an EST OFF command which resets the synthesizer to zero, an address load command LA in which four bits are received from the CPU at pins D4-D7 and transferred to the permanent memories as digits. address via address register 213 and pins AD1-ADD8; a read and branch command RB by which the permanent memory takes the contents of the current address and the next address, and uses them for a branch address; an RDBY byte read command which allows the central processing unit to supply data stored in the permanent memory by the address pin 8 (ADD8) and the data register 212; and an external speech command SEKSXU by which an external speech logic circuit 253 generates a decoder prohibition signal DDIS, inhibiting the control decoder 211 and allowing the central processing unit to input eight data bits into the buffer 2215, by pins DO-D7.

When the synthesizer 10 has begun speaking in response to an SPK command, it continues to do so until the interface circuit 21 receives an EST command, or the gate 207 (Fig. 8a-81) detects a code "energy equal to 15" and restores the conversation register 216 in response to this command. When the synthesizer 10 has started speaking in response to a SPKEXT command, it continues to do so until the gate 207 detects an "energy equal to 15" code or receives an empty buffer command BE produced by the circuit. state logic 2230 (see FIGS. 8a to 8f) and restores the register 216 in response to this command. It thus appears that an "energy equal to 15" code is used as the last frame of data among several frames to produce words, propositions or sentences. The commands LA, RB and RDBY are decoded by the control decoder 211 and are re-coded by the memory control logic circuit 217 to be transmitted to the permanent memories by means of the instruction pins 10-11.

 Conversation register 216 is set to "1" in response to a decoded SPK or SPKEXT command and is reset to "O": (1) during a power-on reset operation (PUC) ) which is done automatically when the synthesizer is energized> (2) by a decoded RST command; (3) by a code "energy equal to 15" in a speech data frame or (4) by a command BE from the state logic circuit 2230. The output signal TALKD is a delayed signal which allows all Speech parameters are introduced into the synthesizer before speech is spoken.

The logic circuit 22 for loading, storing and decoding parameters comprises a parameter input register 205 having a capacity of seven bits which receives serial data from the permanent memories via the logic circuit 2250 of loading of speech, coming from the gate 2251 which receives at its input the data coming from the pin ADD8 in response to a command RD sent to the permanent memory by the instruction pins. A random access memory 203 of coded parameters and condition decoders and registers 208 are connected to receive the data entered in the input register 205. As will be apparent from FIG.
following, each frame of speech data is introduced
in three six-bit parts, through the re
parameter input box 205, to the memory at ac
203, in coded format, in which the frame is memorized momentarily. Each of the coded parameters stored in the memory 203 is converted into a ten-bit parameter by the parameter permanent memory 202, and is stored momentarily in the parameter input register 201.

 As will be explained later with reference to FIG. 6, the data frames may be fully or partially introduced into the parameter input register 205, depending on the length of the particular frame introduced. The condition register decoders 208 respond to particular portions of the data frame to set up repetition registers, zero pitch, zero energy, old height, and old energy registers. the functions of these registers will be described later with reference to FIGS. 8a to 81. The condition decoders and registers 208, as well as different timing signals are used to control the interpolation gates 209. The interpolation gates produce an IN inhibition signal when the interpolation is to be inhibited. a ZPAR zero parameter signal when the parameter is to be reset to zero and an ACP parameter load authorization signal which, among other things, is used to load data from the input register 205 into the parameter direct access memory coded 203.

 The parameters of the output register 201 are applied to the function element 23 for interpolation of the parameters. The speech parameters K1-K11, including the speech energy, are stored in a stack K 302 and a loop E10 304 while the pitch parameter is stored in a pitch register 305. The speech parameters and the energy factor are applied by the recode logic circuit 301 to a matrix multiplier 401 of the excitation filter and generator 24.But it appears that when a new parameter is loaded into the output register 201, is not introduced immediately into the stack 302 or the loop 304, or the register 305, because the corresponding value in the stack 302, the loop 304 or the register 305 undergoes eight cycles of interpolation during which part of the difference between the current value in the stack, the loop or the register and the desired value of this parameter in the output register 201 is added to the stack, loop or register.

Virtually the same logical circuits are used to perform height and energy interpolation, and speech parameters K 1 -K 1 0. The expected value of the output register 201 is applied with the current value of the parameter corresponding to a subtractor 308e
A selector 307 selects the current height from the pitch logic 306, or the current energy, or the coefficient data K from the transfer register KE10 303, according to the parameter currently in the output register 201. and applies it to subtractor 308 and delay circuit 309. This latter introduces a delay between zero and three bits.

The output of the delay circuit 309, with the output of the subtractor 308, is applied to an adder 310 whose output is applied to a delay circuit 311. When the delay of the circuit 309 is zero, the expected value of the particular parameter in the output register 201 is effectively introduced in the stack 302, the loop 304 or the height register 305, as appropriate The delay of the delay circuit 311 is between three and zero bits, three bits when the delay of the circuit 309 is zero, so that the total delay in the selector 307, the delay circuits 309 and 311, the adder 310 and the subtractor 308 are constant. By the delay control of the delay circuits 309 and 311, all, half, quarter or eighth of the difference emitted by the subtractor 308 (i.e., the difference between the expected value and the current value) is added back to the current value of the parameter. By ordering delays as shown in the table
I, a relatively regular interpolation of an eight-phase parameter is made.

The above-mentioned US patent application No. 905,328 describes, with reference to FIG. 7, a speech synthesis filter in which speech coefficients K1-K9 are continuously stored in the stack K, until they are corrected, while the coefficient K11 and the energy of the speech (designated by
A in this patent application) are periodically exchanged. In the parameter interpolator 23, the speech coefficients B1 to K9 are likewise stored in the stack 302 until they are corrected while the energy parameter and the coefficient K10 exchange their place in the stack 302. during a cycle of 20 operating periods of the filter and excitation generator 24. For this purpose, the loop ElO 304 stores the energy parameter and the coefficient E10 and alternately introduces them into the appropriate position of the battery K 302. the transfer register KE10 303 is loaded with the parameter K10 or the energy parameter from the ElO loop 304 or the appropriate speech coefficient K1-K9 from the stack K 302, for the interpolation by the logic circuits 307- 311.

It appears that the recoding logic circuit 301 preferably applies an algorithm to the data coming from the stack K 302, before these data are applied to the multiplier 401. the recoding circuit 301 therefore makes it possible to reduce the dimensions of the multiplier 401, compared to that described in the patent application of
United States of America n 905 328 supra.

 The filter and excitation generator 24 comprises the matrix multiplier 401 whose output is connected to an adder-multiplexer 402. The output of the latter is connected to the input of an adder 404 whose output is connected to a battery delay signal 406 and multiplier-multiplexer 415. the output signal of the delay stack is applied to an input of the adder-multiplexer 402 and a Y-register 403. The output of the Y-register 403 is connected to an input multiplier-multiplexer 415 as well as a logic cut-off circuit 425. The output of the multiplier-multiplexer 415 is connected to an input of the matrix multiplier 401. The filter and excitation generator 24 uses the digital filter described in FIG. United States Patent Application No. 905,328, supra. Various minor interconnections are not shown in FIG. 4b, to clarify, but they will be described in detail next to the freezes 10a, 10b, 11a and llb. The arrangement of the above elements generally corresponds to that described with reference to FIG. 7 of US Patent Application No. 905,328, multiplier 401 corresponds to element 30 ', multiplexer adder 402 corresponds to elements 37b', 37c 'and 37d', doors 414 (FIGS. 11a and 11b) correspond to the element 33 ', the delay stack 406 corresponds to the elements 34' and 35 ', the Y register 403 corresponds to the element 36' and the multiplier-multiplexer 415 corresponds to the elements 38a, 38b, 38c and 38d.

 The voice excitation data is provided by the gate 408 of muffled or audible sounds. As will be explained in more detail below, the parameters introduced into the parameter gate 205 are provided in compressed data format. According to the data compression principle used, when the coded pitch parameter is zero, in the input register 205, it is interpreted as a deaf condition by the decoders and condition registers 208. The gate 408 responds by providing data. randomly from the deaf generator 407 as the excitation input. But when the value of the coded parameter of height is different, this parameter is decoded by the permanent memory 202, loaded into the parameter output register 201 and possibly introduced into the height register 305 "either directly or after the operation of interpolation already described On the basis of the period indicated by the number in the height register 305, a voice excitation is extracted from the permanent oscillation memory 409.

As has been described in the patent application of
In United States of America No. 905,328, the voice excitation signal may be a pulsed function or any other repetitive function, for example a repetitive oscillation function. In the present embodiment, a variable oscillation has been chosen because it tends to reduce the "fuzziness" of the speech produced (because it more accurately reproduces the effect of the vocal chords than a pulsed function). The oscillation is produced repetitively by the permanent memory 409. The latter is addressed by the counter register 410 whose address is incremented by a unit addition circuit 411. The address in the register 410 continues to progress in the addition circuit 411 and it is recirculated by the logic circuit 412 to rest until the amplitude comparator 413 which compares the value of the address transmitted by the addition circuit 411 With the contents of the height register 305 indicates that the value of the register 410 is equal to or greater than the value in the height register 305 and at this time the quit circuit 412 resets the address in the counter to zero. 410. The oscillation function of the permanent memory 409 starts at the zero address and extends to about 50 addresses. The counter register 410 and the permanent oscillation memory 409 are made in such a way that higher addresses at 50 do not cause any part of the oscillation function of the permanent memory 409 to be sent to the mute gate 408. The oscillation function is thus produced repetitively over a period related to the pitch during the sound word. .

 Fig. 5 shows the time relations between the appearances of different timing signals produced in the synthesizer chip 10. It also shows the time relations with respect to the introduction of a new data frame, at the time TD, in the pellet 10, as well as the time relations with the interpolations performed on the introduced parameters, the time relations of the above operations with the periods of the scale filter as well as the relationships between all the aforementioned basic clock signals .

 The synthesizer is preferably made with logic circuits of the pre-load and conditional firing type and, therefore, FIG. 5 shows clock signals 1-4 4 which can be suitably used with these logic circuits. These are two main clock phases 1 and 2 and two pre-charge clock phases # 3 and 4. Phase # 3 goes low during the first half of phase # 2 and therefore performs a load function. prior. A group of # 1- # 4 clock signals is needed to pass a data bit, which is the period.

The periods are designated T1-T20 and preferably each last about 5 microseconds. The choice of a period of the order of 5 microseconds allows, as will appear hereafter, to transmit data by the digital filter at a frequency of 10 kilohertz (that is to say at a period of 100 microseconds) corresponding to a 5 kilohertz frequency response in the digital-to-analog output section 25 of FIG. 4b. But it appears that, depending on the frequency response that is desired and the number of speech coefficients used, and so on the type of logic circuits used, the period or the frequency of the clock signals and the phases of clock of FIG. 5 may be modified
As explained in the aforementioned U.S. Patent Application No. 905,328, the cycle time of the digital filter of the filter and excitation generator 24 preferably comprises 20 T1-T20 periods. For reasons that do not matter here, the numbering of these periods differs from that described in the aforementioned patent application. To make it easier to understand the numbering differences of the periods, the two numbers appear on line 500 of FIG. 5. On this line, the periods T1-T20 which are not in parentheses identify those which correspond to the agreement of the present description. Those which are in parentheses correspond to the agreement of the aforementioned patent application. Thus, the period T17 equals the period (9).

 Reference 501 denotes PC parameter count timing signals. In this embodiment, 13 PC signals are provided, PC = 0 to PC = 12. The first 12 PCs = 0 to PC = 11 correspond to the times when the energy, height and Ki-KI0 parameters are respectively available in the output register 201.

Each of the first 12 PC signals covers two cycles, which are designated A and B. Each cycle starts at period D17 and continues until the next period T17.

During each PC signal, the expected value of the output register 201 is interpolated with the existing value in the K 302 stack of the parameter interpolation 23. During the cycle A, the interpolated parameter is extracted from the stack 302, of the loop ElO-304 or register 305, as appropriate, for a suitable period. During cycle B, the newly interpolated value is fed back into the K stack (or the ElO loop or pitch register). The thirteenth PC signal, PC = 12, is provided for timing purposes, so that the 12 parameters are interpolated once during each interpolation period of 2.5 microseconds.

As has been explained with respect to the parameter interpolator 23 of FIG. 4b and Table IV, 8 interpolations are performed during each introduction of a new data frame in the synthesizer 10, from the memories-12a-12b. This appears under the reference 502 of FIG. 5 which shows the synchronization signals DIVA, DIV2, DIV4 and DIV8. These synchronization signals occur during specific interpolation (IC) counts. Eight of these interpolation counts are provided, ICO-IC7. New data is introduced into the synthesizer during ICO, from the permanent memories 12a-12b. These new expected values of the parameters are then used during the following eight interpolation counts, IG1 to ICO; the existing parameters in the pitch register 305, the stack K and the loop ElO 304 are interposed once during each interpolation count. At the last interpolation count, ICO, the current value of the parameters in the height register 305, the stack K 302 and the loop ElO 304 finally reaches the predicted values, previously introduced towards the last period ICO and, consequently, new ones. The expected values can again be entered as a new data frame. Since each interpolation count is done in a period of 2.5 milliseconds, the period in which the new data frames are entered in the synthesizer pellet lasts 20 milliseconds, or equals a frequency of 50 hertZ
The signal DIV8 corresponds to the interpolation counts in which one-eighth of the difference produced by the subtractor 308 is added to the current values in the adder 310 while, during the signal DIV4, a quarter of the difference is added and so on. .

Thus, during the signal DIV2, half the difference from the subtractor 308 is added to the current value of the parameter in the adder 310, and finally, during DIV1, the total difference is added in the adder 310. has been indicated previously, the effects of this interpolation appear in Table I.

It has already been indicated that new parameters are introduced into the wall synthesizer at a frequency of 50 hertz. It will then be apparent that in the parameter interpolator and the excitation generator 24 of FIG. 4b, the height data, the energy data and the parameters E1-K10 are stored and used as ten-bit binary numbers. If each of the twelve parameters was corrected with a ten-bit number, at a frequency of 50 hertz from an external source, for example the permanent memories 12a and 12b, this would impose a bit rate of 12 x 10 x 50, or 6000 hertz0
Data compression techniques which will be explained below reduce the bit rate required for the synthesizer 10 at a frequency of the order of 1000 to 1200 bits per second. More importantly, the compression that will be described does not significantly degrade the quality of the speech produced compared to the use of uncompressed data.

 Fig. Figure 6 schematically illustrates the principle adopted for data compression. This figure shows four different lengths of data frames. One, represented in A or sound frame, has a length of 56 bits, another, represented in E3 and called muffled frame, has a length of 33 bits, while another, represented in C and called "frame repetition 11, has a length of 11 bits and another still, represented in D, which can be called a frame of zero energy or energy equal to 15, has a length of only 4 bits. data bits for a coded energy parameter as well as 4 coded bits for parameter K7.

Six bits of data are reserved for each of the three coded parameters, two heights, K1 and K2. Five data bits are reserved for parameters K3 to K6. In addition, three data bits are provided for each of the three speech coded parameters K8 = K10 and, finally, another bit designated R is reserved for a repeat bit.

Instead of introducing 10 bits of binary data for each of the parameters, a coded parameter is introduced and converted to a 10-bit parameter by addressing the parameter permanent memory 202 with the encoded parameter. Thus, for example, the coefficient K1 can have any one of 36 different values, depending on the 6-bit code of this coefficient, each of the 36 values being a 10-bit digital coefficient stored in the parameter memory 202.Thus the actual values of the coefficients K1 and K2 may be one of 36 different values while the actual values of the coefficients K3 to K6 may be one of 20 different values. the coefficient K7 can be one of 16 different values and the values of the coefficients
K8 to E10 can be one of 8 different values. The encoded pitch parameter has a length of 6 bits and can thus have one of 64 different values. But only 63 of them reflect actual height values, the 000000 height code being used for desirability. a dull frame of data. the coded energy parameter has a length of 4 bits and can therefore normally have 16 possible values at 10 bits; but a coded energy parameter of 0000 indicates a frame of silence, appearing for example during pauses and between words, sentences, etc. An encoded parameter of energy equal to 1111 (energy equal to 15) is furthermore used to indicate the end of a speech segment, thus indicating that the synthesizer stops speaking.Among the 16 codes available for the coded parameter of 14 are used to designate different levels of 1-bit speech energy.

The coded coefficients K1 and K2 comprise more bits than the coefficients K3-K6, which in turn comprise more bits than the coefficients coded K7 to
K10, because the coefficient K1 has a greater effect on the speech than K2 which, luimeAme, had greater effect on the speech than E3, and so on for the coefficients of lower orders. Thus, tenn account of the greater significance of the coefficients K1 and K2 with respect to the coefficient K8 to K10, more bits are used in the coded format to define the coefficients K1 and
K2 as the coefficients K3-K6 or K7-K10.

 It also appears that the speech data requires more coefficients to correctly represent the speech than the deaf lyrics and, therefore, when deaf frames appear, the coefficients K5 to K11 are not corrected but are simply reduced to zero. The synthesizer knows no dumb frames are emitted when the uncoded pitch parameter equals 000000.

 it has also been found that, during speech, it is often the case that the parameters do not change significantly during a period of 26 seconds more particularly, the coefficients K1-K10 can often remain almost constant. Thus, a repetition frame is used in which a new energy and a new height are introduced into the synthesizer while the K1-K10 coefficients previously introduced remain unchanged. The synthesizer recognizes the 10-bit repetition frame because the repetition bit between energy and height is in state "1" while it is normally in the "O" state. As has already been indicated, it appears pauses between words or at the end of the conversation which are preferably indicated on the synthesizer; these pauses are indicated by a coded energy frame equal to zero and at this time the synthesizer recognizes that only four bits must be sampled for this frame. In a similar way, only four bits are sampled for an energy equal to 15. The use of coded values for speech instead of the actual values only allows the bit rate to be reduced to 55 X 50, ie 2750 bits. per second.

In addition, thanks to the use of frames of varying lengths, as shown in FIG. 6, the data rate can be further reduced to about 1000 to 1200 bits per second, depending on the speaker and the text spoken.

The different parts of the speech synthesizer of FIGS. 4a and 4b will now be described with reference to FIGS. 7A to 14b which detail the lo giqua circuits made on a semiconductor chip, for example
ple, to form the synthesizer 10. The following description, made with reference to the drawings, mentions if
logical signals available in many areas of the world.
cooked. It should be remembered that, in MOS circuits with channel P, a logical "O" corresponds to a negative voltage,
that is Vdd, while a logical level "1" cor
responds to zero voltage, ie Vss.It is necessary
furthermore, remember that P-channel MOS transistors
presented in the above figures are conductive
when a level "O", that is to say a negative voltage,
is applied to the respective grids. When a signal
logic is mentioned without a line above, the signal must be interpreted as a logical state "TRUE" that is to say that a bit "1" indicates the presence of the signal (Vss) while a bit "O" indicates the absence of the signal (Vdd).

Logical signal names with a line above are "FALSE"; that is, a "0" bit (Vdd) indicates the presence of the signal while a "1" bit (Vss) indicates that the signal is not present. It is also well understood that the number 3 in clock-controlled gates indicates that phase 3 is used for a pre-load while a number 4 indicates that phase # 4 is used as a pre-charge timer. An "S" in the door indicates that his command is static.

 Figs. 7a and 7d form a detailed and composite logic diagram of the synchronization logic circuit of the synthesizer 10. The counter 510 is a pseudo-random shift counter comprising a shift register -510a and a feedback logic circuit 510b. The counter 510 counts pseudo-randomly and the outputs "1" and "0" of the shift register 510a are applied to the input section 511 of a programmable timing logic array. The different periods decoded by the programmable logic array are indicated next to these output ligules. Section 511c of the programmable logic synchrohization matrix is connected to a programmable output timing logic array 512 producing different combinations and sequences of timing signals. time, for example T even, T10-T18, etc. Sections 511a and 511b of logical matrix 511 will be described later.

The parameter count in which the synthesizer operates is maintained by a parameter counter 513. The latter has an add-on circuit of one unit and circuits which can react to signals.
SLOW and SLOW D slow mode in another embodiment. In the SLOW mode, the parameter counter
twice the cycle A of the parameter count (for
a total of three cycles A) before entering the cy
B. In other words, the period of the parameter count is doubled so that the parameters applied to the scale filter are corrected and interpolated to half the normal frequency. To ensure that the parameters entered are only interpolated once during each parameter count in the case of slow speech operation, each parameter count comprises three A cycles followed by a B cycle. It should be remembered that, during the A cycle, the interpolation starts and that, during the cycle B, the interpolation begins. interpolated results are introduced again in the stack K 302, in the loop ElO or the height register 305, as the case may be. Thus, the simple repetition of the cycle A has no other effect than to calculate again the same value of a speech parameter but, since it is introduced only once in the stack
K 302, the Ego loop 304 or the height register 305, the results of the interpolation immediately before the cycle E3 are maintained. Therefore, in another embodiment, the speech module can be controlled to speak at a slower speed than the normal speed. In the present embodiment, this possibility is not desired and, therefore, the inputs
SLOW and SLOW D are maintained at Vss.

Since the parameter counter 513 has an add-on circuit of one unit, the results it outputs, PC1-PC4, represent in binary form the count of particular parameters in which the synthesizer operates. PC1O output indicates which cycle, A or
B, the parameter count is found. The decimal value of the parameter count is decoded by the programmable timing logic matrix 514 which is shown next to the matrix 511, with indications such as PC = O, PC = 1, PC = 7, and so on. The relationship between the particular parameters and the value of
PC appears in fig. 6. Output portions 511a and 511b of the programmable logic array 511 are also interconnected with outputs of the timing matrix 514 by the high pass of the transfer signal K (TK) during T9 of PC = 2 or T8 of
PC = 3 or 27 of PC = 4, and so on until TI of PC = 100
In a similar manner, the LDP parameter load synchronization signal goes high for PC = O or PC T1 = 1 or PC = 2 T3, and so on up to PC = 11 T7. It appears that the signal TK is used to control the data transfer from the parameter output register 201 to the subtractor 308, this transfer being done at different times T depending on the count of particular parameters of the counter, in order to ensure that the appropriate parameter is output from the transfer register KE10 303 The LDP signal is used in combination with the parameter input register to control the number of bits that are entered as a function of the number of bits associated with the parameter ae. loaded ;, based on the number of bits of each coded parameter as defined in FIG. 6.

 The interpolation counter 515 includes a shift register and a unit addition circuit for counting the particular interpolation cycle in which the synthesizer operates. The relationship between the particular interpolation count in which the synthesizer operates and the DIVA, DIV2, DIV4 and DIV8 synchronization signals derived therefrom is explained in detail with respect to Fig. 6, and any further explanation would therefore be superfluous. It should be noted, however, that the interpolation counter 515 includes a three bit register 516 which is loaded at T1. The output of the three-bit register 516 is decoded by gates 517 to produce the aforementioned synchronization signals DIV1 to DIV8. The interpolation counter 515 responds to a RESETF signal from the parameter counter 513, allowing the interpolation counter 515 to progress only after PC = 12.

 The fi, 8a to 8m form a composite and detailed diagram of the interface logic circuit 21 between the permanent memories and the central processing unit. The parameter input register 205 is a 16-bit shift register of which most stages have a 2-bit capacity. In the present embodiment, the stages are two bits because the permanent memories 12a and 12b transmit data at half the frequency at which these data are normally transmitted in the synthesizer 10.

 The coded data of the parameter input register 205 is applied on INO-INS lines to the coded parameter direct access memory 203 which is addressed by PC1-PC4 to indicate the coded parameter to be stored. The contents of the register 205 are controlled by the gate 207 every 1, the gate 206 every "O" and the repetition register 208a. The gate 206 checks all the "0" in the 4 least significant bits of the register 205 while the gate 207 checks all the "1" for these same ones.

bits. Gate 207 also responds to signals PCO, DIV1, 216 and PC = 0 so that condition "O" is only monitored during the time when the encoded parameter of energy is loaded into parameter register 205. embodiment, the repetition bit immediately appears before the encoded pitch parameter; therefore, it is controlled during PC = 1 cycle. Height register 208b is set in response to all "O's" in the pitch encoded parameter-and it responds not only to gate 206, but also to two bits of greatest weight of height data on line 222, as well as PC = 1. The pitch register 208b is set when the pitch encoded parameter is 000000, indicating that the speech should be muted.

 The zero energy register 208 is responsive to the output signal of the gate 206 and to the PC = O signal, verifying whether all the "O's" have been introduced as energy coded parameters, and is set in response to this. trial. the old register 208d stores the output signal of the register 208b from the previous frame of speech data while the old energy register 208e stores the output of the register 208c from the previous frame of speech data. the old register 208d and the register 208b of zero height are compared in comparison gates 209c for the purpose of producing an INHIBAIT inhibition signal. This signal inhibits interpolations, which is desirable during changes in muted speech or muted speech, so that the new speech parameters are automatically introduced into the E-302 stack, the E10 loop 304 and the speech register. height 305, rather than being interpolated more slowly in these memory elements. In addition, the contents of the old energy register 208e and the energy register 208c equal to zero are checked by the NAND gate 209d in order to inhibit interpolation during a transition from a silence frame to a speech frame. The output signals of the NAND gate 209d and the gates 209c are applied to a NAND gate 209e whose output is inverted by an inverter 236 to produce the INHIBAIT signal. The registers 208a to 208c are brought to rest by the gate 225 and the registers 208d and 208e are brought to rest by the gate 226. When the excitation signal is deaf, the coefficients K5-K10 are set to zero, as is This is done in part by the action of gate 209b which produces a ZPAR signal when the height is zero and when the parameter counter is above 5, as indicated by PC5 since the programmable logic matrix 514.

Figs. 8a to 8m also show a control register 210 which comprises three bistable circuits 210a, b and c which lock the data to the pins D1, D2 and
D3 in response to a command load authorization LDCE signal. The contents of the control register 210 are decoded by the command decoder 211.

When the command decoder 211 decodes a command LA, the 4 data bits at the pins D7, D6, D5 and D4 of the data bus line 17 are locked in the address register 213. The address value which
is in the address register 213 is coupled by
the buffers 214 to the pins ADD1-ADD8, to the permanent memories 12a and 12b. In addition, the LA control is applied to an RB / LA logic circuit 250 which is used to generate the instruction pin signal Il to control the permanent memories 12a and 12b. The logic circuit 250 also produces the LAFIN signal to indicate the end of the LA command.

When the command decoder 210 decodes a command
RDBY byte read, the data stored in the permanent memories 12a and 12b are accessible to an external CPU. The command RDBY causes the reading of the following 8 data bits in the permanent memories 12a and 12b, in the data register 212. The RDBY command is introduced in the gate 291 of the data register control circuit 290. The output of the gate 291 is used to control the buffers 212a and to transmit the data in the data register 212 to the pins DO-D7 of the data bus line 17.If the RDBY command is immediately preceded by an LA control at gates 271 and 272 of machine state circuit 270, the resulting signal passing through gate 274 produces a signal at instruction pin I03 at gate 273. This output signal 103 is used to initialize the counter in the permanent memories 12a and 12b. The RDBY command is then delayed after it passes through the gates 275a and 275b, by a timer register 276a, b and c. The latter is positioned at time 92 and returned to idle at time 217. This delay gives sufficient time for the initialization of the counter of the permanent memories 12a and 12b. The signal RDBY is also applied to the gate 278 of the machine state circuit 270. The output signal of the gate 278 is applied to the gates 277 and is used to generate the RDBYEN signal of the byte read permission at the gate. Gate output 279. This signal is applied to the gate 292 of the data register control logic circuit 290 at odd times T and is used to produce the signals at the I02 instruction pin which output the data from the data. permanent memories 12a and 12b in the data register 212.If the RDBY command is not immediately preceded by an LA command (when the counter of the permanent memories 12a and 12b is already initialized), the command
RDBY is entered at the gate 281 of the machine state circuit 270, and the signal at the instruction pin I03 and the delay corresponding to the timer 276 are not used.

If the command decoder 211 decodes a RB command for reading and branching; the synthesizer 10 can indirectly address areas of the permanent memories 12a and 12b. This is done by applying the RB command to the RB / LA logic circuit 250 which produces the signals to the instruction pins I1 and I04, which are transmitted to the permanent memories 12a and 12b. In addition, the command RB is applied to the timer RE 252 which delays it by 240 microseconds and then produces an RBFIN end of read and branch signal. The RUPIN signal indicates that the read and connect instruction has been executed by the memories. 12a and 12be The control RE is also applied to the machine state circuit 27OD at the doors 272 and 282. But since the permanent memories 12a and 12b produce a signal inside the instruction pin 10 during the operation reading and connecting, the gate 282, through the gate 274, inhibits the signal of the instruction pin 10 normally produced by the machine state circuit 270
When the command decoder 211 decodes an RST quiescent command, this command is used either alone or in combination with the power-up PUC signal to initialize or restore various circuits in the synthesizer assembly 100 to rest.
When the command decoder 211 decodes an SPK conversation command, the synthesizer 10 produces synthetic speech using the speech coded parameters stored in the permanent memories 12a and 12b. This is done by the talk authorization circuit 251. which generates a talk authorization SPEN signal used to set the talkback circuits 216a, b and c. The flip-flop 216a produces a talk state TALES signal used throughout the synthesizer 10 to indicate that speech is being produced. The flip-flops 216a, b, and c remain in the i state until they are reset to "0" by the flip-flop circuit 232a or 232b, in the case of: 1) a power-up signal PUC and / or quiescent RST; 2) an "energy equal to 15" signal detected by the gate 207; or 3) in the external speech mode, which will be described later, where a signal is produced indicating that the buffer is empty and that the control decoder 211 is inhibited. The SPK command is also applied to the gate 281 of the machine state circuit 270 in which it is used to produce an end-of-conversation signal SPKFIN.

 When the command decoder 211 detects an external conversation SPKEXT command, the synthesizer goes to the external conversation mode. In this mode of operation, coded speech parameters from an external source, preferably from the central processing unit of a commercial or large computer, are introduced on the DO-D7 pins of the data bus line 17. The speech encoded parameters at the D0-D7 pins are input to a first-in, first-out buffer 2215 which is organized as a 16 x 8 parallel input serial-output memory. The coded speech parameters are introduced into the memory 2215 by the control circuit 2210. The latter transmits a multiplet of data each time a signal WBYI! The byte write signal is outputted from the output logic circuit 260. The speech data of the memory 2215 is serially introduced into the parameter input register 205 during the external conversation mode and the speech synthesis takes place. . This operating mode proceeds as follows.

The external conversation circuit 253 whose input receives the SPEXT signal produces a decoding interlock signal DDIS which prohibits the control decoder 211, thus ensuring that the data at the DO-D7 pins are processed as speech data. rather than instructional data. The external conversation circuit 253 also generates an external conversation limit signal SPKEE which clears the memory 2215 by initializing the counter 2220 and producing a quiescent signal CLR to the control circuit 2210. The memory 2215 is also associated with a state logic circuit 2230 that produces two signals. The low buffer signal BL is generated each time the buffer 2215 is half full. This signal is used to indicate to the central processing unit that the synthesizer is to be serviced. State circuit 2230 also produces an empty buffer BE signal which indicates that buffer 2215 is empty. The signal BE is used to bring the conversation register 216 to rest by the gate 232b. The signal
DDIS is also used by the input / output circuit 2240 to produce a serial offset enable signal SSE which allows the control circuit 2210 to serially shift speech data out of the buffer 2215 via the circuit. 2250 of speech loading, and in the parameter input register 205.The interface logic circuit 21 between the permanent memories and the central processing unit is also associated with an input / output logic circuit 260 and An interrupt circuit 2260. The input / output circuit 260 generates a command charge authorization command LDCE that allows the command register 210 to lock a command. This is done by a bistable circuit 261 which is set to "1" by the power-on signal PUC or by the "end" signals of the different commands 5, the bistable circuit 262 which is set to i by the output of the bistable circuit 261 as well as the DDIS prohibition signals of WS write-select decoders and the availability DISP.Therefore the control charge enable signal is generated at the output of bistable circuit 263 when: (1) none command is running; (2) the command decoder 211 is not prohibited; (3) a write selection signal WS is present; and (4) the synthesizer 10 has just detected the write selection signal (DISP at high level). The input / output circuit 260 also generates the byte write signal WDYG which allows the control circuit 2210 to load an 8-bit speech coded multiplet to the upper level of the buffer 2215. This is done using a a bistable circuit 264 which is set to "1" by a write select command WS1 when the following conditions exist: (1) the command decoder 211 is prohibited by a decoding prohibition signal DDIS, indicating that a External speech control has been executed: (2) the -OC level of buffer 2215 is empty; and (3) the synthesizer 10 is no longer executing a previous command (the DISP signal is high).

The byte write signal WBYU is then output at the output of the gate 265. The input / output circuit 260 also generates the signal DISP at the output of the gate 267 in response to a selection input signal. read or write selection from the central processing unit. When the signal DISP is high, the central processing unit is linked to the speech module until the signal DISP is interrupted by the gate 266. This latter brings this signal to zero when any of the signals As follows: (1) a WBYT signal is generated at the output of the gate 265 indicating that the data byte on the data bus line 17 has been read in the buffer 2215; (2) the signal SR2 is generated by the buffers 212f-g of the data register 212 via the data register control circuit 219 indicating that the status signals produced by a read select command have been issued (3) the signal SR1 is transmitted by the buffers 212a-h of the data register 212 via the control circuit 290 indicating that the 8-bit byte requested by a read-out signal preceded by a signal of byte reading was produced or (4) the LDCE command produced by the gate 263 is applied to the gate 270 indicating no control was locked in the control register 210. The interruption logic 2260 produces the interrupt signal INT for notifying the central processing unit of a change of state of the synthesizer 10.The three status signals controlled by the central processing unit are the empty buffer signal BE, the low buffer signal EL e The signals BE and BL are produced by the state circuit 2230 and are transmitted via the buffers 212f and 212g. The signal TALKST is produced by the talk switch circuit 216a and the signal TALKST is generated by the talk switch circuit 216a. is transmitted by the buffer 212ho
A change of state of the synthesizer 10 resulting in a change of aa signal BE, BL or TALKST is detected by the gates 2261, 2262 and 2263 of the interrupt circuit 2260 and the result is that an interrupt signal INT is produced. 226-5 is used to interrupt the INT signal after receiving a signal SR2 indicating that the state residing in the frame 212f-ha has been read by the central unit of the signal. treatment, or that the quiescent signal has been received.

 Figs. 9a to 9d form a detailed composite scheme of the parameter interpolator circuit 23-. The stack E 203 has ten registers which each store ten bits of information. Each small square represents a bit of memory, according to the convention adopted under reference 330.

The contents of each shift register is recirculated by the recirculation gates 314 to the control of a recirculation control gate 315. The stack K 302 stores speech coefficients E1-E9 and momentarily stores the coefficient K10 or the energy parameter, as in the speech synthesizer of FIG. 7 of the above-mentioned United States Patent Application No. 905,328. The data transmitted from the K stack 302 to the recode logic circuit 301 at different periods are shown in Table II. Table III of the aforementioned patent application shows the data emitted by the battery K of FIG. 7.Table II of this patent application differs from Table III of the present specification in that: (1) the recoding circuit 301 receives the same coefficient on the lines 32-1 to 32-4, on the lines 32- 5 and 32-6, on the lines 32-7 and 32-8 and on the lines 32-9 and 32-10 because this circuit 301 responds to two bits of information for each bit to which it has been answered by the multiplier in matrix of the aforementioned patent application: (2) because of the difference in nomenclature of time period explained with reference to FIG. 5; and (3) due to the delay associated with the recoding circuit 301.

 The recoding circuit 301 connects the stack K 302 to the matrix multiplier 401 of FIGS. 10a to vi. the circuit 301 comprises four identical coding stages 313a313d of which only one, 312a, is shown in detail. The first stages of the coding circuit 313 differ from the stages 312a-312d since there is of course no restraint as happens at the input A of the stages 312a312d from a lower order stage. The recoding circuit emits +2, -2, +1 and -1 to each stage of the five-stage matrix multiplier 401, except for the zero stage which receives only the outputs -2, +1 and -1. In fact, the recoding circuit 301 allows the matrix multiplier to process, in each of its stages, two bits instead of one bit of information, by applying the Booth algorithm. This algorithm is explained in "2henry and Application of Digital Signal Processing", published by Prentice-Hall 1975, pages 517-518.

The coefficient K10 and the energy parameter are stored in the ElO loop 304. Preferably, this loop comprises a twenty-stage series shift register; ten stages 304a of the loop 304 are preferably connected in series and ten further stages 304b are also connected in series, but also have parallel outputs and inputs to the battery K 302.The appropriate parameter, energy or the coefficient
K10, is transferred from the loop 304 to the stack 302 through the gates 315 that respond to a NOR gate 316 by transferring the energy parameter of the loop 304 to the stack 302 at time T10 and transferring the coefficient K10 from loop 304 to stack 302 at time 220. The NOR gate 316 also controls recirculation control gate 315 to inhibit recirculation in stack K 302 as the data is transferred.

 The transfer register KE10 303 facilitates the transsert of the energy or speech coefficients K1-K10 which are stored in the loop E10 304 or in the stack K 302 to the adder 308 and the delay circuit 309, via The register 303 has nine stages with paired inverters and a tenth stage consisting of the selector 307 and the gate 317 to facilitate the transfer of ten bits of information from the loop E10 304 or the stack K 302. Data is transferred from the K stack 302 to the register 303 by the transfer gates 318 which are controlled by a transfer signal K (DK) produced by the decoding portion 511b of the programmable matrix 511 of FIGS.

7a to 7d. Since the particular parameter to be interpolated and thus shifted in the register 303 depends on the particular count of parameters in which the synthesizer operates and since the particular parameter available to be transmitted from the stack K 302 is a function of a period of time. In which the synthesizer operates, the signal TE appears in T9 for the height parameter, in T8 for the parameter Ri, in T7 for the parameter K2 and so on, as shown in FIGS. 7a to 7d. The energy parameter or coefficient K10 is transferred from loop E10 304 to register 303 through gates 319 in response to a signal TE10 produced by matrix 511. After each interpolation, that is, say during the cycle
B, data is transferred from the register 303 to: (1) the stack K 302 by the doors 318 to the control of the signal TK, in which case the recirculation doors 314 are closed by the door 315, or (2) to the ElO 304 loop through the 319 doors.

 A ten-bit height parameter is stored in a pitch register 305 which consists of a neat-stage shift register with recirculation elements 305a for storing another bit. The height parameter recirculates normally in the register 305 through the gate 305a, except when a newly interpolated height parameter is output on the line 320 to the control of the pitch interpolation logic circuit 306. The output of the pitch register 305 (PTO) or the output of the register 303 is applied to the gate 317 by the selector 307. The selector 307 is also controlled by the circuit 306 to normally couple the output of the register 303 with the gate 317. except when the height is to be interpolated. Circuit 306 responds by transmitting the height to adder 308 and delay circuit 309 during cycle A of PC = 1 and returning the interpolated height value on line 320 during the cycle. PC = 1 to the register 305. The gate 317 is controlled by a register 321, only to provide height, energy or coefficient information to the adder 308 and the delay circuit 309 during operation. interpolation. Since the data is transferred in series, the information transfer can start during part A and PCO can go to state "1" during the transfer of information from register 303 or 305 to adder 308 or delay circuit 309 and, therefore, the gate 317 is controlled by a bistable circuit 321 of cycle A which is set to "1" with PCO at the instant when a transfer signal TK ElO (TE10) or TP transfer of height is produced by the programmable logic array 511.

 The output signal of the gate 317 is applied to the adder 308 and to the delay circuit 309. The delay of the latter depends on the state of the signals DIV1-DIV8 produced by the interpolation counter 515 of FIGS. 7a to 7do Since the gate 317 transmits the data with the least significant bit first, delaying the data in the delay circuit 309 by a selected duration, and applying the output signal to the adder 310 with the output signal of the subtractor 308, the circuit 309 brings all the more delay that the value of the difference from the subtractor 308 and added again by the adder 310 is smaller. The delay circuit 311 connects the adder 310 to the registers 303 and 305. The delay circuits 309 and 303 can introduce up to three delay bits and, when the adder 309 is at the maximum delay, the delay circuit 311 is at the same time. minimal delay, and vice versa. A NAND gate 322 connects the output of the subtractor 308 to the input of the adder 310. The gate 322 is controlled by the output signal of an OR gate 323 which, in turn, responds to the INHIBIT signal from the inverter 236 (Figs 8a to 8m).

The gates 322 and 323 zero the output of the subtractor 308 when the signal INHIBIT appears, unless the interpolation counter is at ICO, in which case the current values in the stack K 302, the loop E10 304 and the register P 305 are fully interpolated with the new expected values, into a single-phase interpolation. When a muted frame (Fig. 6) is supplied to the speech synthesis pad, the coefficients K5 to K10 are set to zero under the effect of the gate 324 which connects the delay circuit 311 to the shift register 325 of which the outlet is connected to the doors 30a and 303 '. Gate 324 is controlled by the zero parameter signal
ZPAR produced by the door 209b (Fig. 8a to 8m).

 Gate 326 prevents the offset in portion 304b of loop E10 304 when a newly interpolated energy value or K10 is introduced in portion 304b of register 303. The gate 327 controls the transfer gates connected to the stages of the register 303, these stages being prohibited to the serial shift of the data when the signal TK or TE10 goes high during the cycle A, that is to say when the register 303 is to receive data from the stack K 302 or the key E10 304 to the control of the transfer gates 318 or 319. The outputs of the gates 327 are also connected to the different stages of the shift register 325 and to a gate which torque 303 'with register 303, so that up to three bits that can follow the ten most significant bits after an interpolation operation can be reset to zero.

 Figs. 10a to 10c form a detailed composite scheme of the matrix multiplier 401. These multipliers are sometimes referred to as "pipeline multipliers". By way of example, such a multiplier is described in Granville E. Ott's "1Pipeline Multiplier" published by the University of Missouri.

 The matrix multiplier 401 has four stages, stage O to stage 4, and a delay stage. The input of the multiplier 401 receives the signals MRO-MR13 from the multiplier-multiplexer 415. MRi3 is the bit of greatest weight while MRO is the least significant bit. Another multiplier input receives the aforementioned signals-+2, -2, +1 and -1 from the recoding circuit 301 (Figs 8a-8c). the output of the multiplier 401, P13-Po, is applied to the adder-multiplexer 402. In the present embodiment, the least significant bit, PO, is always in the "1" state as this establishes the average of the zero-cut error rather than plus or minus half the least-significant bit, which would result from simply cutting a number complemented by two.

 The matrix multiplier 401 is represented as boxes designated A-1, A-2, B-1, B-2, B-3 or B-C.

The particular logical elements that appear in these boxes appear in fig. 10c and are not repetitively represented for simplicity. The cell elements A-1 and A-2 constitute the zero stage of the multiplier and therefore each react to the -2, +1 and -1 signals from the decoder 313, and also react to the MR2-MR-13 signals. When a multiplication is made in the multiplier 401, the largest weight bit is always maintained in the elements of the left column while the partial sums are continuously shifted to the right. Since each stage of the multiplier 401 operates on two bits, the partial sums are shifted two positions to the right.

Thus, no type A box receives the data inputs MRO and MR1 on the first floor. Moreover, since each box of the multiplier 401 responds to two bits of information from the stack K 302 through the recoding circuit 301, each box also responds to two bits from the multiplier-multiplexer 415. being inverted by the inverters 430 and also being provided in the true state to the B-type boxes.

 Figs. 11a to 11d form a detailed composite scheme of the excitation filter and generator 24 (outside the multiplier 401) and the output section 25. In the filter and excitation generator 24, an adder 404 is connected to receive at a input the true or inverted output of the multiplier 401 (see Figs. 10a-10d) on the lines PO-P13 through the adder-multiplexer 402. The other input of the neural add 404 is connected by the distributor-multiplexer 402 for receiving the output of the adder 404 (at T10-T18), the output of the delay stack 406 on the lines 440-453 (at T20-T7 and T9), the output of the register Y 403 (at 8) or an "O" from the pre-charge gate 420 (at T19 when no conditional discharge is applied to this input). The reason these signals are applied at these times is apparent from the examination. of fig. 8 of the aforementioned patent application; ; it must of course be remembered that the designations of the periods differ as has been explained with regard to f, ig. -5.

The output of addictor 404 is applied to delay stack 406, multiplexer-multiplexer 415, delay gates 414, and summator-multiplexer 402. Multiplier-multiplexer 415
comprises delay gates 414 of a period which are equivalent to gates 34 'of FIG. 7 of the aforementioned patent application. A Y stable circuit 403 is connected to receive the output of the delay stack 406. The multiplier-multiplexer 415 selectively applies the output of the bistable circuit 403, the delay gates 414, or the excitation signal of the bus line 405, at the input MRO-MR13 of the matrix multiplier 401. The inputs D0-D13 of the delay stack 406 come from the outputs of the adder 404. The circuits of the adder-multiplier 402 of the adder 404, bistable circuit Y 403, multiplexer-multiplexer 415 and circuit 414 of. one-bit delay only appear in detail for the least significant bit, framed by dashed line A.

The thirteen bits of greater weight of the filter also have identical circuits flanked by an elongated rectangle designated "A." The logic circuits for each parallel bit processed in the filter are not shown in detail for simplicity. The parts of the filter which process the bits of greater weight than the least significant ones differ from the circuits shown for the elements 402, 403, 404, 415 and 414 only by the interconnections made with the breaking circuits 501 and the bus line. 405 which connects the gate W 408 and the permanent memory chip 409. In this respect, the output of the gate W 408 and the pellet 409 is only applied to the inputs I13-16 and, therefore, the input designated Ix in the dotted line of reference A is not necessary for the six least significant bits of the filter, and the output of the bistable circuit Y 403 is only applied to the ten most significant bits YL13 to YL4 and, by therefore, the YLx connection in the reference line is not necessary for the four least significant bits of the filter.

The delay stack 406 has 14 nine-bit shift registers each of which has clock-controlled inverters 4 and 3. As explained in the aforementioned patent application, the delay stack 406 corresponds to the shift register 35 '. of fig. 7 of this application and is only delayed at certain periods. This is done at the control of the logic circuit 416 by which clock signals # 1B-# 4B are generated from the timing signals T10-T18 from the programmable matrix 512 of FIGS. 7a to 7d
Clock buffers 417 of circuit 416 are also shown in detail in FIGS. lia at 11d.

 The delay stack 406 is nine bits long whereas the shift register 35 'of FIG. 7 of the aforementioned patent application is eight bits long; this difference results from the fact that the input of the delay stack 406 is connected to the output of the adder 404 rather than to the output of the delay circuit of a period 414. Of course, the input of the delay battery 4.06 could be connected to the outputs of the delay circuit 414, the associated synchronization being modified to correspond to that described in the aforementioned patent application.

 The data is preferably manipulated in two's complement in the delay stack 406, the matrix multiplier 401, the adder 402, the adder-multiplexer 402, the Y-register 403 and the multiplier-multiplexer 415.

 The deaf generator 407 is a random noise generator comprising a shift register 418 with a feedback term provided by feedback circuits 419, producing pseudo-random terms in the register 418, an output is taken therefrom and is applied to gate W 408 which also responds to the OLDP signal from the bistable circuit 208d of FIGS. 8a to 8m. The old-stage register 208d controls the gate 408 because the zero-height register 208b changes state immediately when the new speech parameters are entered in the register 205. But since this occurs during the interpolation count ICO and since during the muted condition the new values are not interpolated in the stack K 302, the loop E10 304 and the pitch register 305 until the next ICO period, the speech excitation value can not change from periodic excitation from oscillation memory 409 to random excitation from deaf generator 407 until eight interpolation cycles are performed. Gate 420 performs the NOR combination of the output of gate 408 and the largest bit of the drive signal, 113, so that the sign bit changes randomly during speech mute. Gate 421 in fact forces the larger bit of excitement signal 112 to state "1" in the speech-to-speech conditions. Thus, the doors 408, 420 and 421 have the combined effect of producing a random change of associated sign with a constant equivalent decimal value of 0.5 applied to the filter of the filter and excitation generator circuit 24.

 During a speech, the oscillation memory 409 produces an eight bit output on the lines I6-I13 to the filter. This output consists of 41 successively changing values which, when plotted as a curve, represent a variable oscillation function. The contents of memory 409 are shown in Table III. This memory is made in such a way as to invert its outputs and, consequently, the data are stored in complemented format. The oscillation function value and the complemented value stored in the oscillation memory are expressed in hexadecimal notation complemented by two. The memory 409 is addressed by an eight bit register 410 whose contents are normally corrected during each cycle of the filter, by the unit addition circuit 411. The output of the register 410 is compared with the contents of the pitch register 305 in an amplitude comparator 403 in order to reset to zero the contents of the register 410 when it is equal to or greater than that of the register 305. The memory 409, which is shown in more detail in FIGS. 14a and 14b, is arranged so that addresses greater than 110010 cause the transmission of all 11011s on the lines I13-I10, to the mutitiplier-mutitipîexeur 415.

"O" is also stored at address positions 41-51. Thus, the oscillation can be extended to eventually occupy all addresses up to position 50.

 Figs. 12a, 12b form a detailed composite diagram of the random access memory 203. The latter is addressed by an address on PC1 -PC4, this address being decoded in a programmable logic matrix 203a and defining a coded parameter which must be introduced into the memory 203. The memory 203 stores the twelve decoded parameters, whose length varies between three bits and six bits, according to the decoding principle described with reference to FIG. 6. Each cell, reference B, of the random access memory 203 is shown in more detail in FIG. 12b.A read / write control logic circuit 203b is controlled by the signals T1, DIVI, PCO and the parameter load enable signal to write to the memory 203 during the cycle A of each parameter count, during the Zero interpolation count2 with the authorization of the parameter loading signal from circuit 209a of FIGS. 8a to 8c. The data is entered in the random access memory 203 on the INO-INS lines coming from the register 205, as shown in FIGS. 8a and 8b, and the data are transmitted on the lines CRu-CR5 to the permanent memory 202 as appears in the above figures.

Figs. 13a, 13b and 13c form a logic diagram of the permanent memory 202. The latter is preferably a permanent-to-virtual memory of the type described in United States Patent No. 3,934,233. from the memory 202 and the parameter counter 513 are applied to address buffers 202b which are shown in detail under the reference A. The NOR gates 202a
used in 202b address buffers are represented
The outputs of the address buffers 202b are applied to a decoder X 202c or a decoder Y 202d. The permanent memory is divided into ten sections, denoted by the reference C, one of which is shown in more detail. The output line of each of the sections is connected to a register 201 by inverters, as shown in FIGS. 8a and 8b. The decoder x selects one of 68 decoding lines X while the decoder Y 202d verifies the presence or the absence of a transistor cell between two neighboring diffusion lines, as is explained in more detail in the patent. United States of America No. 3,934,233 cited above. The data that is preferably stored in memory 202, in this embodiment, is shown in Table IV.

 Figs. 14a and 14b form a composite diagram of the permanent oscillation memory 409. The permanent memory 409 is addressed by address lines A0-A8 from the register 410 of FIGS. 11a, 11b and it transmits information on the lines I6-I11 to the multiplier-multiplexer 405 and on the lines II and I2 to the gates 421 and 420, all shown in Fig.1la and 11b. As has already been explained with regard to these latter figures, the permanent oscillation memory emits all "0's" when a predetermined count is reached in the register 410 which, in this case, equals a decimal number 51. Permanent memory 409 includes a Y decoder 409a that responds to the address on the lines and and A1 (and Ao and A1) and an X 409b decoder that responds to the address on the lines A2 to Ag (and A2 to A).

5
The memory 409 also includes a bistable circuit 409c which is set to "1" when the decimal number 51 is detected on the lines A0-A5, depending on the line 409c from the decoder 409e. The latter also decodes a "0" on the lines A0-A8 to bring back to "0" the bistable circuit 409c. The permanent memory 409 also comprises a synchronization circuit 409f which allows the data to pass through the gates 409g at the period T12. At this time, the decoder 409e checks whether a decimal number 0 or 51 is present on the lines of A0-A8. If any of these conditions occur, the flip-flop circuit 409c, which is a static bistable circuit, changes state.

An address bistable circuit 409h is set at "1" at period 13 and at "0" at period T11. The bistable circuit 409h allows the bistable circuit 409, when it is at i'1 ", to force a decimal figure 51 on the lines
A0-A5. Thus, for addresses greater than 51 in the address register 410, the address is first sampled at the period T12 to determine whether it was reamed to zero by the quit circuit 412 (freezes). 12a12b) for the purpose of returning the bistable circuit 4O9c to "O", whereas, if the address has not been reset to zero, any address introduced on the lines A0-A-8 is written at T13 by the logic circuit 409j Of course, the position 51 of the permanent memory 409 must store all "0s" on the output lines 16-111, IM1 and IM2.

Thus, thanks to the logic circuits 409c, 409h and 409j, addresses of a predetermined value, in this case a decimal number 51, are simply checked to determine if a quiescent has occurred, without allowing addressing the matrix of the memory cells by the decoders 409a and 409b. The addresses between the decimal values O and 50 normally address the permanent memory by the decoders 409a and 409b. The permanent memory array is preferably of the virtual mass type described in U.S. Patent No. 3,934,233. As indicated, Table III lists the contents of the memory 409. The Variable oscillation is located at addresses 00-40 while "0" are placed at addresses 41-510
Figs. 11a to 11d also show in detail the cut-off circuit 425 and the digital-analog converter. The cut-off circuit 425 has two-to-one data conversion circuits on the lines YL13-YL4, in offset bit data. The logic circuits 425a and 425b control the largest-order bit of the Y-register 403 on the line YL13 in the purpose of determining the sign bit and producing the clipping signals CLIPO and CLIP1. The logic circuit 425a produces the CLIPO signal and drives all the inputs of the digital to analog converter 426 with "O" s when
YL13 is a "1" and when YL12 or YL11 is an "O". The logic circuit 425c controls YL13-YL11 for the conditions opposite to those indicated above, and produces the NORM signal when no break is made. This amplitude cut function actually truncates the bits of larger ones. weight on YL11 and YL12. It should be noted that this is an unorthodox cut, as normally the least significant bits are truncated in most other circuits when a cut is made. But in this circuit, large positive or negative values are in fact clipped; It has become apparent that, more importantly, digital speech information, when its amplitude is smaller, is actually magnified in a ratio of 4 by this cutoff arrangement. the logic circuit 425d converts the two complement data from the Y registers 403- on the lines YL10 YLt into simple amplitude information on the lines
D / A6-D / A0.The D / A7 line is connected to YL12 because, when the conditions are such that no break occurs,
YL12 and YL11 are identical.

 Table V shows the effects of the cut-off system adopted. When the outputs YL13-YL4 produce a decimal number greater than +127, the inputs of the digital-to-analog converter are all driven to state "1", and the output current is zero. When YL13-YL4 produces a decimal number less than -128, the inputs of the digital to analog converter are all driven with "O" and the output current is 1500 microamperes.

The midpoint occurs when YL13-YL4 equals -1 in decimal notation, and the converter output current is 250 microamperes. Thus, the converter 426 produces an output analog signal that varies around a statistical level (750 microamps in the present embodiment). In addition, when the speech module stops speaking, the TALKST signal is used to turn the output current to zero in order to save power consumption.

 The D / A7-D / Ao outputs are connected to the digital-to-analog converter 426. These outputs are preferably connected to the gates of eight MOS switching components 429a. The D / A7-D / A9 outputs are also connected by inverters 429b to the gates of eight BITOS 429c switching components. The sources of the components 429a are connected to Vss and their sources to Vref. Vref is a predetermined voltage calculated to bias current sources 429d to operate in saturated mode. The drains of the components 429a and 429c are connected in common point to each branch of the converter 426 and the gates of the power source components.

429d. The electrodes of these are connected in parallel with the source of each component connected to Vss. The drains of the components 429d are connected to an output pin by a 1.8 kilohm resistor, to a low frequency amplifier and a speaker of a commercial or consumer type calculator.

 It should be noted that the converter 426 converts the sign and amplitude data from YL13 to YL4 into an analog signal which can be considered as an alternating signal with a fixed component. It also appears that digital-to-analog converters such as those described herein can be applied to other embodiments than speech synthesis circuits.

Preferably, the permanent memories 12a and 12b are of the decatit type and illustrated in the aforementioned US patent application 901 394.
It is understood that many modifications may be made to the embodiment described and illustrated by way of non-limiting example without departing from the scope of the invention.

ANNEX TABLE I
The synthesizer 10 includes interpolation logic circuits to perform an almost linear interpolation of the twelve speech parameters at eight points of each frame, i.e. once every 2.5 milliseconds. The parameters are interpolated one at a time, at the choice of the parameter counter. The interpolation circuits calculate a new value of a parameter from its current value (ie the value currently stored in the stack K, the pitch register or the E-10 loop) and the value provided stored in coded form in the random access memory 203 (decoded by the permanent memory 202) .The value calculated by each interpolation is indicated below,
where P. is the current value of the parameter,
P. is the new value of the parameter,
Pt is the expected value,
N. is an integer determined by the interpolation counter.

The values of N for specific counts of
Pi-Po terpolation and values (Po is the ini value
Pt-Po tial of the parameter) are as follows
INTERPOLATION COUNT N. Pi in
Pt-Po
1 8 0.125
2 8 0.234
3 8 0.330
4 0.498
5 4 0.623
6 2 0.717
7 0.859
0 1 1,000 TABLE II
DATA ISSUED BY BATTERY K 302 TO RECOVERY CIRCUIT 301 PER PERIODS
RELEASE
PERIODS
K BATTERY
BIT LINE T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27
LSB 32-1 K2 K1 A K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 32-2 K2 K1 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 32-3 K2 K1 A K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 K2 K2 K1 K1 K8 K6 K5 K5 K4 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 K3 K3 K2 K9 K8 K7 K6 K5 K5 K4 K3 K1 K10 K9 K8 K7 K6 K5 K4 K3 K3 K2 K1 K8 K7 K6 K5 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 K3 K2 K9 K9 K8 K7 K6 K5 K4 K3 K3 K1 K1 K10 K9 K8 K7 K6 K5 K8 K3 K3 K2 K1 K8 K8 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6 K9 K5 K4 K3 K9 K9 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6
MSB 32-10 K5 K4 K3 K2 K1 A K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6
TABLE III
PERMANENT MEMORY CONTENT OF VARIABLE OSCILLATIONS
ADDRESS FUNCTION VALUE MEMORIZED VALUE
OSCILLATION (COMPLEMENTEE)
00 00 FF
01 2A D5
02 D4 2B
03 32 CD
04 B2 4D
05 12 ED
06 25 DA
07 14 EB
08 02 FD
09 E1 IE
10 C5 3A
11 02 FD
12 5F A0
13 5A A5
14 05 FA
15 0F F0
16 26 D9
17 FC 03
18 A5 5A
19 A5 5A
20 D6 29
21 DD 22
.22 DC 23
23 FC 03
24 25 DA
25 2B D4
26 22 DD
27 21 DE
28 OF F0
29 FF 00
30 F8 07
31 EE he
32 ED 12
33 EF 10
34 F7 08
35 F6 09
36 FA 05
37 00 FF
38 03 FC
39 02 FD
40 01 FE
TABLE IV
PARAMETERS DECODES
EP CODE K1 K2 K3 K4 K5 K6 K7 K8 K9 00 000 000 205 2DA 23F 1EF 28B 32B 20A 33D 386 01 001 00E 207 2FG 250 2F2 2A5 350 2F8 38B 3C9 02 002 00F 209 315 265 324 2C2 377 318 3E0 00F 03 003 010 20B 336 27F 25C 2E4 3A0 33A 036 053 04 004 011 20F 359 29E 39F 309 3CA 35F 089 095 05 006 012 213 37E 263 3D8 332 3F5 386 005 0D2 06 008 013 218 3A4 2EF 019 3SE 021 3AE 117 108 07 00B 014 21F 3CC 321 059 38D 04B 3D7 14F 137 08 010 015 227 3F4 359 096 3BF 075 001 09 017 016 231 01C 395 0CF 3F1 090 02B 0A 021 017 23E 044 305 103 024 0C3 054 0B 02F 018 24E 06C 016 130 056 0E7 07D 0C 03F 019 262 091 057 157 087 108 0A3 0D 055 01A 27A 0B6 094 178 0B5 126 0C8 0E 072 01B 296 008 0CE 193 0E0 142 0EA
OF 000 01C 2B8 0F8 102 1A9 107 15B 10A 10 01D 2E0 116 202 202 202 202 11 01E 30E 131 20A 20A 20A 20A 12 01F 341 14A 139 139 139 139 13 020 379 160 13E 13E 13E 13E 14 022 3B5 174 15 024 3F3 186 16 026 031 196 17 028 06E 1A4 18 029 0A8 1B0 18 02B 0DD 1BB 1A 02D 10D 1C5 1B 030 137 1C0 1C 031 15C 1D4 1D 033 17B 1DA 1E 036 194 1FD 1F 037 1AA 1E6 20 039 202 202 21 03C 20A 20A 22 03E 139 139 23 040 13E 13E 24 044 25 048
26 04A
27 04C
28,051
29 055
2A 057
2B 05A
2C 060
2D 063
2E 067
2F 06B
TABLE IV (continued)
PARAMETERS DECODES
EP CODE Ki K2 K3 K4 K5 K6 K7 K8 K9
30,070
31,075
32 07A
33 07F
34,085
35 08B
36,091
37,097
38 09D
39 0A4
3A 0AB
3B 0B2
3C 0BA
3D OC2
3E OCA
3F 0D3
TABLE V
REGISTER Y OUTPUT; ENTER EXIT
DIGITAL-ANALOG
ANALOGIC MIGROAMPERES
YL13 YL12 YL11 YL10 YL4
0 1 OX 11111111 0> +127 0 1 OX 11111111 0
O 0 1 X 11111111 0 127 0 0 O 1111111 11111111 0 126 0 0 0 1111110 11111110 5.86 +1 0 o 0 0000001 1000000i 738 0 0 0 0 0000000 10000000 744

<tb> -1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1111111 <SEP> 01111111 <SEP> 750
<tb> -2 1 1 1 1111110 01111110 755.8 -128 1 1 1 0000000 00000000 1500 <-128 1 1 OX 00000000 1500
1 O 1 X 00000000 1500
1 OQX 0000Q000 1500 # No output, level of rest

Claims (22)

REVEETDICATIOETS  1 - Speech synthesizer characterized in thatii comprises a receiving device (L8) which receives an input signal from an external control device (19), a first memory (12) which permanently stores a first encoded data group, a second memory (22) which momentarily stores a second group of encoded data, said second group of encoded data being provided by said external controller (19), a synthesizer processor (leu) which converts the data encoded into a digital speech signal, a selector (11) selectively applying one of said first and second coded data groups to said synthesizer processor (10) in response to a control signal provided by said controller an external device (19) and a conversion device (25) of said digital speech signal into an analogue speech signal.  2 - synthesizer according to claim 1, characterized in that said first memory is a permanent memory (12a, 12b).  3 - synthesizer according to claim 1, characterized in that said second memory is a shift register (205).  4 - speech synthesizer according to claim 1, characterized in that said synthesizer processor (10) comprises a controlled digital filter (24).  5 - synthesizer according to claim 4, characterized in that said coded data consist of reflection coefficients used to control said digital filter (24).  Speech synthesizer, characterized in that it comprises a reception device (18) which receives an input signal from an external control device (19). a first memory (12) which storically stores a first group of encoded data, a second memory (22) which momentarily stores a second group of coded data consisting of speech encoded parameters provided by said external controller (19); ), a third memory (13) which stores a third group of coded data, said third memory being disposed in a module with a plurality of electrical contacts, a connector (3) for momentarily interconnecting said plurality of electrical contacts of said module with said speech synthesizer, a synthesizer processor (10) which converts the encoded data into a digital speech signal, a selector (11) which selectively applies one of said first, second and third coded data groups to said synthesizer processor (10) in response to a signal control device provided by said external control device (19) and a disp conversion device (25) of said digital speech signal into an analog speech signal.  7 - synthesizer according to claim 6, characterized in that said first memory is a permanent memory (12a, 12b).  8 - synthesizer according to claim 6, characterized in that said second memory is a shift register (205).  9 - synthesizer according to claim 6, characterized in that said third memory is a permanent memory (13a, 13b).  10. Synthesizer according to claim 6, characterized in that said synthesizer processor (10) comprises a controlled digital filter (24).  11. Synthesizer according to claim 10, characterized in that said coded data consist of reflection coefficients used to control said digital filter (24).  12 - A computing device capable of producing synthetic human speech, characterized in that it comprises a computer input device (18), a central processing unit (19), an amplifier unit for sound and speaker (5, 20), and a synthesizer responsive to control signals generated by said central processing unit (19), said speech synthesizer including a first memory (12) which permanently stores a first group of data coded, a second memory (22) which momentarily stores a second group of coded data, said second group of coded data being provided by said central processing unit (19), a synthesizer processor (10) which converts the data into digital data a selector (11) selectively applying one of said first and second coded data groups to said synthesizer processor (10) in response to a command signal provided by said central processing unit (19), a conversion device (25) which converts said digital speech signal into an analog speech signal, and a coupling device (18) of said conversion device with said amplifier assembly sound and speaker (5, 20).  13 - computing device according to claim 12, characterized in that said speech synthesizer is arranged in a module (1) with several electrical contacts, and which can other momentarily connected to said computer input device by said several electrical contacts .  14 - computing device according to claim 12 characterized in that said first memory is a permanent memory (12a, 12b).  15 - computing device according to claim 12, characterized in that said second memory is a shift register 205).  16 - computing device according to claim 12, characterized in that said synthesizer processor (1O) comprises a controlled digital filter (24).  A synthesizer according to claim 6, characterized in that said encoded data consists of reflection coefficients used to control said digital filter (24).  18 - Interface circuit between a control device providing instructions of variable length and a much slower memory device triggering and executing said instructions of variable length, interface circuit characterized in that it comprises a first circuit (212) ) connected to said memory device and for detecting the end of the execution of a variable-length instruction and supplying a control signal in response thereto, a second circuit (211) connected to said first circuit for triggering a new instruction in response to said control signal, a third circuit (217) connected to said second circuit for detecting the triggering of said new instruction and producing a second control signal in response thereto, and a gate circuit for selectively coupling said control device to said memory device to drive it crazy executing said variable length instruction, and deleting the coupling between said controller and said memory device in response to said control signal.  19 - Circuit according to claim 18, characterized in that said control device is a central processing unit (19) of a computer.  The circuit of claim 18, characterized in that said memory device is part of a speech synthesizer.  21. A circuit according to claim 18, characterized in that said control device (19) also provides fixed length instructions and said memory device also executes said fixed-set instructions.  22. A circuit according to claim 18, characterized in that said first circuit (212) further comprises a timer which determines the end of the execution of said fixed length instructions and which delivers said control signal in response thereto. - tion.  23 - A computing device capable of producing synthetic human speech, characterized in that it comprises a central processing unit (19) which discharges from. variable tongger speech instructions a speech synthesizer (10) that executes said variable length instructions and produces an analog speech signal according to these instructions, a sound amplifier and loudspeaker assembly (5, 20). ) which converts said speech analog signal into an audible sound, a control circuit (11) interposed between said central processing unit (19) and said speech synthesizer (10), said control circuit comprising a first circuit (212) coupled to said speech synthesizer and for detecting the end of execution of a variable length speech instruction and producing a control signal in response thereto, a second circuit (211) - coupled to said first circuit and enabling triggering a new instruction in response to said control signal, a third circuit (217) coupled to said second circuit for detecting the triggering of said new instruction and producing a second control signal in response thereto and a gate circuit for selectively coupling said central processing unit (19) with said speech synthesizer (10) to provide said instructions variable length speech and suppressing the coupling between said central processing unit and said speech synthesizer in response to said second control signal.  A device according to claim 23, characterized in that said central processing unit (19) also generates fixed length speech instructions said speech synthesizer WO) also executing said fixed length speech instructions.  25. The device as claimed in claim 24, characterized in that said first circuit also comprises a timer which determines the end of the execution of said fixed length speech instructions and which delivers said control signal in response to this detection.  26- Device according to claim 23, characterized in that it further comprises an input device by the user so that the operator can selectively control said central processing unit (19)  27 - Device according to claim 26, characterized in that said input device by the user consists of a keyboard.