FR2483656B1 - Ordinateur comportant des circuits de manipulation de bits - Google Patents

Ordinateur comportant des circuits de manipulation de bits

Info

Publication number
FR2483656B1
FR2483656B1 FR8110707A FR8110707A FR2483656B1 FR 2483656 B1 FR2483656 B1 FR 2483656B1 FR 8110707 A FR8110707 A FR 8110707A FR 8110707 A FR8110707 A FR 8110707A FR 2483656 B1 FR2483656 B1 FR 2483656B1
Authority
FR
France
Prior art keywords
computer
handling circuits
bit handling
bit
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8110707A
Other languages
English (en)
Other versions
FR2483656A1 (fr
Inventor
Ismail Ibrahim Eldumiati
Michael Kent Maul
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of FR2483656A1 publication Critical patent/FR2483656A1/fr
Application granted granted Critical
Publication of FR2483656B1 publication Critical patent/FR2483656B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/762—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
FR8110707A 1980-06-02 1981-05-29 Ordinateur comportant des circuits de manipulation de bits Expired FR2483656B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/155,317 US4525776A (en) 1980-06-02 1980-06-02 Arithmetic logic unit arranged for manipulating bits

Publications (2)

Publication Number Publication Date
FR2483656A1 FR2483656A1 (fr) 1981-12-04
FR2483656B1 true FR2483656B1 (fr) 1987-06-26

Family

ID=22554951

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8110707A Expired FR2483656B1 (fr) 1980-06-02 1981-05-29 Ordinateur comportant des circuits de manipulation de bits

Country Status (6)

Country Link
US (1) US4525776A (fr)
JP (1) JPS5794852A (fr)
DE (1) DE3121046A1 (fr)
FR (1) FR2483656B1 (fr)
GB (1) GB2079502B (fr)
NL (1) NL8102650A (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748580A (en) * 1985-08-30 1988-05-31 Advanced Micro Devices, Inc. Multi-precision fixed/floating-point processor
US4775952A (en) * 1986-05-29 1988-10-04 General Electric Company Parallel processing system apparatus
JP2565495B2 (ja) * 1986-08-27 1996-12-18 株式会社日立製作所 デ−タ処理システム
FR2656710A1 (fr) * 1989-12-29 1991-07-05 Radiotechnique Compelec Microcontroleur pour l'execution rapide d'un grand nombre d'operations decomposable en sequence d'operations de meme nature.
US5327571A (en) * 1990-04-03 1994-07-05 Advanced Micro Devices, Inc. Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right
JPH06230960A (ja) * 1993-01-29 1994-08-19 Mitsubishi Electric Corp データ処理回路
JP2932963B2 (ja) * 1994-01-21 1999-08-09 モトローラ・インコーポレイテッド 効率的なビット移動能力を有するデータ・プロセッサとその方法
US6061783A (en) * 1996-11-13 2000-05-09 Nortel Networks Corporation Method and apparatus for manipulation of bit fields directly in a memory source
US7031776B2 (en) * 2001-06-29 2006-04-18 Optobionics Methods for improving damaged retinal cell function
US20050033202A1 (en) * 2001-06-29 2005-02-10 Chow Alan Y. Mechanically activated objects for treatment of degenerative retinal disease
US8275978B1 (en) * 2008-07-29 2012-09-25 Marvell International Ltd. Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982229A (en) * 1975-01-08 1976-09-21 Bell Telephone Laboratories, Incorporated Combinational logic arrangement
US4212076A (en) * 1976-09-24 1980-07-08 Giddings & Lewis, Inc. Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former
US4194241A (en) * 1977-07-08 1980-03-18 Xerox Corporation Bit manipulation circuitry in a microprocessor

Also Published As

Publication number Publication date
DE3121046A1 (de) 1982-03-11
NL8102650A (nl) 1982-01-04
GB2079502A (en) 1982-01-20
DE3121046C2 (fr) 1992-03-05
JPH0447335B2 (fr) 1992-08-03
US4525776A (en) 1985-06-25
JPS5794852A (en) 1982-06-12
FR2483656A1 (fr) 1981-12-04
GB2079502B (en) 1984-07-11

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Legal Events

Date Code Title Description
ST Notification of lapse