FR2474762A1 - DEVICE FOR ELECTRICALLY JOINING THE ENDS OF A FIRST GROUP OF SEMICONDUCTOR LINES SUBSTANTIALLY PARALLEL, AT THE ADJACENT END OF A SECOND GROUP OF SEMICONDUCTOR LINES, SUBSTANTIALLY PARALLEL AND IN THE SAME NUMBER - Google Patents

Abstract

THE INVENTION CONCERNS A DEVICE FOR ELECTRICALLY JOINING THE ENDS OF A FIRST GROUP OF SEMICONDUCTOR LINES SENSITIVELY PARALLEL TO ADJACENT ENDS OF A SECOND GROUP OF SEMICONDUCTOR LINES SENSITIVELY PARALLEL AND IN EQUAL NUMBER. ACCORDING TO THE INVENTION, A NUMBER OF METAL CONTACTS 44A-44D, EACH OF WHICH COVERS THE ADJACENT ENDS OF A LINE IN EACH GROUP 32A-32B ARE ARRANGED IN THE DIRECTION IN WHICH THE PARALLEL LINES EXTEND TO ENABLE FOR THESE CONTACTS 44A-44D TO COVER THE ENDS OF THE LINES WHILE OCCUPYING THE MINIMUM NECESSARY SPACE IN A DIRECTION SENSITIVELY PARALLEL TO THAT IN WHICH THE LINES EXTEND. THE INVENTION APPLIES IN PARTICULAR TO DEAD MEMORIES WITH AN INTEGRATED CIRCUIT.

Description

The present invention relates to memories

  mcrtescu "ROM" on integrated circuit.

  The cuROM read-only memories are used in electronic circuits to store information and perform logical functions. In particular, they are used in digital equipment, including minicomputers and microprocessors. In order to increase the economy of the manufacture of the ROMs and to reduce the size of the general systems employing them, it is advantageous to have the greatest possible number of memory bits per integrated circuit chip. Consequently, it is desirable to reduce the area used for each storage cell, a storage cell being the part of the integrated circuit that stores a single bit

  of information. The memory cells are generally

  in an x-y memory arrangement with a decoder circuit located along the x axis of the arrangement for

  choose a particular column of memory cells

  and an additional decoder circuit located along the y-axis to select a particular row of cells so that the intersection of the decoded row and column gives a particular bit of information.

which can be accessed.

  The size of the cells in the memory arrangement determines the density of the cells in the x or y direction, i.e. how the rows and columns of the cells can be approximated. The interval is called the "step" of the arrangement. It should be noted that the "pitch" of the rows may differ from the "pitch" of the columns depending on how the arrangement is implemented and the rules

  particular designs that are used.

  In this description, the term "rules

  design "specifies the rules that define the dimensions of the minimum width of a line and the minimum space between the lines that can be obtained in any

  reliability by the technology in use.

  Until now, ROMs were commonly implemented using a MOS transistor for each cell, the MOS transistor being set to a state

  driver or non-driver. The arrangement of the agencies

  memory using such prior cells requires the presence of contact areas between a layer

  metal and an underlying line of epitaxial silicon.

  Such metal-silicon contacts are added to the size of the memory arrangement, directly affecting the size of the chip. This was not previously a problem, because the ultimate limit on the spacing of rows and columns of cells in the arrangement was usually not determined by the size of the cells but by the size of the decoding circuit

  placed adjacent to the x and y edges of the arrangement.

  It is desirable to maintain the circuit

  decoder "in step" with the rows and columns of the agency-

  for well-known reasons. Accordingly, it is desirable to reduce the size of the decoder circuit so that the decoders correspond to the pitch of the cells in the memory arrangement, thereby decreasing the ultimate size of the chip. Given that a decoder circuit requires a number of gates, and that each gate requires a number of transistors, the pitch of the decoder circuit available to date was much greater than that at which the cells in the arrangement could be arranged. Thus, most of the efforts made to date in the development of ROM memories concerned designs to reduce the space required by the circuit

decoder.

  The present inventors have found a way

  to increase the effective pitch of the memory cells.

  This method can be used to substantially increase the effective pitch of the memory cells in the arrangement by a power of 2, a power of 4, a power of 8, and so on. In addition, the present inventors have studied a new memory arrangement where the cells can occupy the minimum space allowed by the design rules in use. Thus, the combination of the new memory arrangement with the new method to increase the effective pitch of the cells in the arrangement, gives a ROM where the decoder circuit can be constructed of traditional devices, and yet the completed chip will have many more cells than memory that a ROM built in a traditional way using the same

pellet surface.

  According to the invention, an arrangement of

  memory and an associated decoding scheme. The agence-

  It consists of a series of oxide-coated, minimum width, parallel silicon epitaxial lines where the minimum space between adjacent lines permitted by the design rules is used. Covering the epitaxial silicon lines and being orthogonal thereto, there is a series of doped polycrystalline silicon lines that are parallel and of minimum width. The epitaxial silicon lines are all doped to have the same

  type of conductivity and the polysilicon lines

  crystalline are all doped to have the opposite type of conductivity. The number of intersections, looking from above, polycrystalline silicon lines with epitaxial silicon lines will be the product of the number of silicon epitaxial lines "n" by the number of polycrystalline silicon lines, "mu. There will be "n" times "m" intersections At each intersection, a "flooded contact" diode may be formed by removing the oxide from the epitaxial silicon line before depositing it over the polycrystalline silicon line.

  memory is therefore composed of a series of inter-

  sections that can be selectively programmed to have either a diode or an open circuit between a given polycrystalline silicon line and the underlying epitaxial silicon line. The arrangement therefore requires the minimum space allowed by the design rules for a maximum number of storage cells. In order to detect the presence or absence of a diode at a particular intersection, an attempt is made to pass the current through a selected polycrystalline silicon line and to detect this outgoing current through a selected epitaxial silicon line. If the attempt is successful,

  this means that a diode is present at the intersection.

  On the other hand, if the attempt does not succeed, then there is no diode at this intersection. As will be obvious to those skilled in the art, the current flow attempt is made compatible with the polarity of the buried or flooded contact diodes which can

to be present.

  Design rules that require a minimum epitaxial silicon line width ("bit line" of 7 / c- <and a minimum interval between the lines of 4 - determine that the pitch of the columns of the cells in the arrangement can to reach only 11, W. Similarly, a minimum width of a polycrystalline silicon line ("word line") of 3, p- with a minimum space between

  4J lines between the polycrystalline silicon lines

  determines that the steps of the rows of cells in

  the arrangement can reach only 7 / ...

  Given the fact that until now there was no known way to build a decoder

  to correspond to a step of the rows of 7 p-, the

  The high density buried contact memory described herein could not be used to manufacture a high density ROM without the multi-stage decoder circuit.

  unique studied by the present inventors.

  The decoders in a ROM serve the function of selecting a particular bit in the memory arrangement. This is usually accomplished in the manner previously described. Typically, the total number of bits in a ROM is a factor of 2, so an individual bit

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  can be chosen by specifying its address as a binary number. In particular, the total number of bits in the memory array, i.e., "n" times "m", is usually 2k, where k is the number of bits in the binary address available to specify

  the particular memory location that needs to be read.

  Typically, "n" and "m" are also powers of 2.

  Thus, if n is equal to 2i, then m is equal to 2 (k-i).

  In order to select a particular location in the memory for reading in the arrangement, one of the 2 rows is selected, each having 2 (k-i) columns. Then, one of the 2 (k-i) columns is chosen to address the desired bit. A common method for selecting a desired bit is to have a line selector selecting one of the 2 lines of words and another line selector choosing one of the 2 (k-i) lines of bits. Thus, a selector of "1 des2in" lines is typically used as a word line decoder and a selector of "1 des2 (ki) n lines is typically used as a bit line decoder. These lines are generally implemented using 2i NAND gates with i inputs and inverters, there is no known way to make a selector 1 des2i.

  lines at a step of 7 / - (for any given value of i).

  It would be particularly useful if the actual pitch of the memory arrangement could be a certain multiple of 7 / A *. According to the present invention, the effective pitch of the rows of cells in the arrangement may be a factor

  arbitrary rate of 2 multiplied by 7 / L, that is to say 14

  crons, 28 microns, 56 microns, etc. Given the fact that the present inventors can construct a word decoder having a pitch of 28d / with a final stage that converts the pitch of the rows of 7., into a step of 28? while simultaneously producing an output of 1 of 4, it is possible to produce a memory pellet having a very high cell density to which [escrresponds an associated decoder circuit. Similarly, the actual step of

  columns can be increased by any desired power of 2.

  The invention will be better understood, and other purposes, features, details and advantages thereof

  will become clearer during the description

  explanatory text which will follow with reference to the accompanying schematic drawings given solely by way of example illustrating an embodiment of the invention and in which: - Figure 1 dnne a schemabloc of the ROM according to the present invention; FIG. 2 is a partial schematic and partly in plan view of the ROM, describing its memory arrangement and associated features; and FIGS. 3 to 7 are cross-sectional views, taken along line 3-3 of FIG. 2,

  illustrating how the ROM is made.

  Referring now to Figure 1, there can be seen a block diagram of the ROM 10 constructed according to the present invention. The ROM 10 consists of an x-y memory arrangement 12 of 2k memory cells, having 2i word lines and 2 (k-i) bit lines. In order to extract a single information bit from the arrangement 12, it is necessary to address both the bit line and the word line associated with a particular cell in the x-y arrangement 12. As a consequence, an address comprising k bits must be applied to an address register 14. From the register 14, two bits are extracted and placed on a word decoding line 16 and connected to a word address decoder 19. The decoder 19 is connected to a series of word pre-decoders 18. Each word pre-decoder according to the preferred embodiment of the invention is a selector of 1 of the 4 lines of a type which will be described below. . Word pre-decoders or word line selectors 18 may be designed to produce a selection of 1 of the 4 lines in the 28 / 'step previously

  indicated, as will be better described below.

  From the address register 14, i-2 bits are applied4

  by a word decoding line 20, to a word decoder 22.

  The decoder 22 is a selector of 1 of2 (i-2) lines.

  The decoder 22 has the function of choosing one of the

  Decoders 18. Each of the pre-decoders 18 of this particular embodiment is connected to 4 word lines of the arrangement 12. Based on the 2 bits on the word pre-decoding line 16, the decoder of FIG. Word address 19 forces each of the pre-decoders 18 to choose one of the four lines of words to which they are connected. The decoder 22

  simultaneously chooses one of the word pre-decoders 18.

  As a result, we use i bits to choose one of the

  2i lines of words in the arrangement 12 in x-y.

  Similarly, 2 bits of the address register 14 are applied, by a bit pre-decoding line 24, to a bit address decoder 25. The decoder 25 is connected to a series of bit pre-decoders 26. Each pre-decoder 26 is a selector of 1 of the 4 lines connected to 4 bit lines in the embodiment described. The remaining k-i-2 bits in the register 14 are applied by a bit decoding line 28 of the address register to the decoder.

  bit 30 which is a selector of 1 of 2 (k-i-2) lines.

  As a result, k-i bits of the address are used to choose one of 2 (kii) bit lines present in

the arrangement 12.

  According to the decoding description above,

  k bits placed in the register 14 are used to choose one of the 2 memory cells present in the arrangement 12. The pre-decoders 18, 26 are intended to match the pitch of the decoders 22, 30 in the step of 12 while simultaneously assisting the process

  decoding. As described above, the pre-

  decoders 18, 26 of this embodiment are selectors of one of the 4 lines. However, it will be obvious

  to those who are competent in this area

  decoders 18, 26 may be selectors of one of the

  8 lines or selectors from 1 of 16 lines.

  Accordingly, pre-decoders 18, 26 which are selectors of 1 of the 4 lines as described herein, should be considered representative rather than exhaustive.

  Like pre-decoders 18, 26, there are

  word line selectors 17 and bit line deselectors 27 connected to the same word lines and bit lines as associated pre-decoders 18 (word line selectors) and 26 (bit line selectors). The deselectors 17, 27 are intended to inhibit 3 of the 4 lines that are not connected to the memory cell that is addressed. The deselectors 17 are connected to the word decoding line 16 by a word line descrambler address decoder 29 and the bit line deselectors 27 are connected to the bit decoding line 24 by an address decoder. Line de-line

bits 31.

  Referring now to Figure 2, there is shown a top view and partially schematic of

  the ROM 10, built according to the present invention.

  For simplicity of explanation, the memory arrangement 12 is an x-y arrangement having 4 word lines 32a-32d and 8 bit lines 34a-34h. The preferred embodiment ROM is constructed using silicon-on-sapphire (SOS) technology, where an epitaxial silicon layer is drawn over an insulating substrate, typically sapphire. The bit lines 34a-34h consist of P + type epitaxial silicon, and the 32a-32d word lines consist of N + type polycrystalline silicon. When the arrangement 12 is constructed, the epitaxial silicon bit lines 34a-34h are covered with an oxide layer. Typically, a layer of thermal silicon dioxide is drawn on the bit lines 34a-34h. The arrangement 12 is then programmed by removing the oxide, typically by etching into buffered hydrofluoric acid (HF), portions of the bit lines 34a-34h where intersections will be formed with the

  Word lines 32a-32d and where diodes are desired.

  Thus, when the polycrystalline silicon word lines 32a-32d are deposited and defined on the epitaxial silicon bit lines 34a-34h, diodes are formed by contact between the word lines 32a-32d and the bit lines 34a-34b. 34h at particular intersections. Interactions

  particular sections where diodes are formed corresponding to

  to the data programmed in the ROM like this

  will be obvious to those who are competent in this area.

  The function of the ROM is to store the information in binary form. The ROM works by indicating the presence or absence of a diode when a particular memory address is chosen. As will also be apparent to those skilled in the art, the term "memory address" indicates the binary code that identifies a particular intersection of a word line 32 and a bit line 34, that is, to say one

particular cell.

  Continuing to refer to Fig. 2, the bit lines 34a-34h extend downward beyond the x-y memory arrangement 12 in the bit pre-decoders 26a, 26b. The address decoder 25 of the particular embodiment shown in FIG. 2 comprises, in part, four NAND gates 40a-40d that drive the pre-decoders 26a, 26b. The pre-decoders 26a, 26b consist of 4 polycrystalline silicon bit pre-decode lines 36a-36d which cover the bit lines 34a-34h. As described above, lines 34a-34h consist of P + type epitaxial silicon lines. However, below the intersections indicated by an "x", where a polycrystalline silicon bit pre-decode line 36a-36d covers an epitaxial silicon bit line 34a-34h, the epitaxial silicon bit lines are doped to be of N-type conductivity. Accordingly, each bit pre-decoder 26a, 26b acts as a one-pole and four-position switch, if a negative potential is imposed on only one of the lines 36a-36d in a given time. By

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  for example, if the line 36a is maintained at a negative potential while the other lines 36b, 36c and 36d are maintained at the maximum positive potential of the chip, only the lines 34a and 34e will be connected to the outputs 38a, 38b of the pre-decoders, respectively. Thus, by appropriately exciting the bit pre-decoder lines 36a-36d, the predecoders 26a, 26b will each have

  a single output line 38a, 38b connected to the arrangement 12.

  Given that the pre-decoders 26a, 26b can be formed with the same rules of geometry and design as the arrangement 12, the pre-decoders 26a, 26b can be built "in step" with the arrangement 12 of memory in xy. In the preferred embodiment of the invention, there is a 4 to 1 decrease in the effective pitch of the bit lines 34a-34h relative to the pitch of the output lines of the pre-decoders 38a, 38b. Similarly, we could get a reduction of 2 to 1, a reduction of 8 to 1

  or any other desired reduction using the pre-

  bit decoders according to the invention.

  When bit pre-decoding has been accomplished, "out of step" decoding of outputs 38a, 38b may be

  made. In the present embodiment of the invention,

  It is assumed that a decoder can be constructed with a pitch four times greater than the pitch of the columns of the arrangement 12. Accordingly, further decoding of the output lines 38a, 38b can easily be accomplished.

  with an effective reduction of the step from 4 to 1.

  The decoder 25 consists of a series of two-input NAND gates, 40a-40d, the outputs of which are connected to the pre-decoder lines 36a36d, and two inverters 41a, 41b, the inputs and outputs of which are connected. at the inputs of the NAND gates 40a-40d. The decoder 25 is used to appropriately drive the lines 36a-36b which form the MOS transistor gates where they intersect the bit lines 34a-34h at the intersections designated by the "x's". The decoder 25 requires two bits of the memory address, b0 and b1, to choose one of the four pre-decoder lines 36a-36d. Following the reduction from 4 to 1 of the effective pitch of the bit lines 34a-34h to the effective pitch of the pre-decoder output lines 38a, 38b, the lines 38a, 38b can be decoded by a conventional circuit (indicated by the reference 30 in Figure 2). The decoder 30 has a single output line 33. As will be understood by those skilled in the art, the decoder 30 of the embodiment shown in FIG. 2 will require 1 bit of the memory address, b2, to select the one of the two output lines 38a, 38b and to connect the output line

  chosen at the output line 33 of the decoder.

  Referring now to the word decoding process of the embodiment shown in FIG.

  fig 2, those who are competent in the field recognize

  It is desirable that the mfot decoding process be undertaken in a manner equivalent to the bit decoding process just described. However, the same type of decoding circuit can not be used because the bit lines 34a-34h of the arrangement 12 are epitaxial silicon lines which are formed in the drain, source and channel regions of the transistors. isolated gate field in bit pre-decoders 26a, 26b as previously explained. Moreover, the word lines are polycrystalline silicon lines that can not be used to form the drain, source and channel regions of transistors

  field effect with insulated door to form a pre-

  word decoder of the type used to decode the lines

bits.

  In order to remedy this situation, and to use, for the word pre-decoding, a circuit equivalent to that used for bit pre-decoding, word line extensions 42a-42d are formed of epitaxial silicon.

  of the P + type at the same pitch as the word lines 32a-32d.

  The adjacent ends of the extensions 42a-42d and 32a-32d word lines are electrically joined by

  metal contacts staggered or staggered 44a-44d.

  The contacts 44a-44d are staggered to allow them to cover the width of the lines 32a-32d and the extensions 42a-42d while taking the minimum amount of space needed in the direction in which the word lines 32a-32d and the extensions 42a-42d extend. The staggered metal contacts 44a-44d thus form an ohmic contact, and yet they are not short-circuited with each other. Thus, the staggered metal contacts 44a-44d form a connection "at the pasn between the polycrystalline silicon word lines 32a-32d and the extensions of the epitaxial silicon word lines 42a-42d, and they make it possible to implement a pre-decoder of the word in exactly the same way as the bit pre-decoders 26a, 26b have previously been implemented, therefore the pre-decoder 18 uses the polycrystalline silicon lines 43a-43d in the same way as the 26a-26b bit decoders use

  polycrystalline silicon lines 36a-36d. Meadow-

  decoder 18 is functionally equivalent to the pre-

  decoders 26a, 26b and no further explanation will be given. Moreover, since there are only four word lines 32a-32d in the present embodiment of the invention, the pre-decoder 18 performs all the decoding

  word, so no additional decoder is required.

  It will be noted that two bits of the memory address, b3 and b4, are used to decode the word lines 32a-32d to select one of them and connect it to the word sorue line 45. necessary word address decoder 19, which works in the same way as the decoder

  bit address 25 explained above, is schematically

  Figure 2. Those skilled in the art will understand that the decoder circuit 19

  can be identical to that of the decoder 25.

  Based on the foregoing description of the

  The address scheme used to select a particular address in the arrangement 12 requires a 5-bit address to address the 32 memory cells in the arrangement 12. As will be understood by those skilled in the art, 25 is equal at 32, the number of cells in the arrangement 12. Referring to FIGS. 1 and 2, it can be seen that in the embodiment described in FIG. 2, 2 bits (b0 and b1) of the address are used. to 5 bits for the pre-decoding of the bit line, 1 bit (b2) of the address for the decoding of the bit line and 2 bits of the address (b3 and b4) for the pre-decoding of the bit line line of words (which is also the decoding of the word line in this example). So, using the notation that was previously used, k is equal to 5,

  and i is 2 for the ROM described in FIG.

  It is not desirable to leave electrically "floating" lines as a floating line can switch to an unknown potential that could interfere with the proper operation of the circuit. As a result, the lines of

  bits 34a-34h extend upward above the agency

  12 in the bit line deselector 27 whose function is to connect the 3 of the 4 bit lines which are not

  not chosen at a known and positive potential of the pellet.

  In the embodiment of the invention shown in FIG. 2, the de-selector 27 links the bit lines 34 which are not selected to the potential.

  highest positive of the pellet, ie Vdd.

  The de-selector 27 is similar to the pre-decoders 26a, 26b

  because it consists of 4 polysilicon lines

  crystal 46a-46d which cover the bit lines 34a-34h. As previously described, the lines 34a-34, h consist of epitaxial silicon lines of the P + type. However, below the intersections indicated by an "x" where one of the polycrystalline silicon descrambler lines 46a-46d overlaps one of the epitaxial silicon bit lines 34a-34h, the epitaxial silicon bit lines are doped to be of N-type conductivity in order to form P-channel MOS transistors. Accordingly, the descrambler 27 acts as a four-position switch which connects three lines of each group of 4 bit lines to the highest positive potential of the chip, i.e. Vdd. The 3 lines among the 4 bit lines that are connected to Vdd are the 3 lines that the pre-decoders 26a, 26b would have.

otherwise left floating.

  The bit line descrambler 27 is controlled by an address decoder 31. The decoder 31 of the preferred embodiment of the invention has a circuit similar to that of the bit decoder 25 except that the gates

  NAND 40a-40d are replaced by NOR gates 54a

  54b and that inverters 39a, 39b are connected to give the NOR gates 54a-54d inverted inputs relative to each other.

  at the inputs of the NAND gates 40a-40d, respectively. Similarly, the word line deselector 17 in the embodiment of

  the invention which is represented in FIG. 2 connects the lines of words which are not chosen to the highest positive potential of the pellet,

  that is, Vdd. The deselector 17 is similar to

  decoder 18 because it consists of 4 polycrystalline silicon lines 48a-48d which cover the extensions of the word lines 52a-52d. As previously described, the word lines 32a-32d of the arrangement 12 consist of N + type polycrystalline silicon lines. As a result, the ends of the word lines 32a-32d are connected by staggered metal contacts a-50d to the P + 52a-52d-type epitaxial silicon word line extensions for the reasons explained above. Below the intersections indicated by "XI, where one of the polycrystalline silicon de-latch lines 48a-48d overlaps one of the extensions

  52a-52d, the extensions are doped to be

  N-type voltage to form P-channel MOS transistors. Accordingly, the descrambler 17 acts as a four position switch which connects 3 rows of each group of 4 word lines to the highest positive potential of the wafer, i.e. Vdd. The 3 lines of the 4 word lines that are connected to Vdd are the 3 lines that the pre-decoder 18 would otherwise have left floating. The descrambler 17 is controlled by a word line descrambler address decoder 29. Those skilled in the art will recognize that the circuit for

  the decoder 29 of the preferred embodiment of the invention

  It can be identical to the one used for the bit line descrambler address decoder 31. Similarly, the circuit used for the bit decoder 25 can also be used for the bit address decoder.

  word 19 in this particular embodiment.

  As a specific example, in order to address the memory cell placed at the intersection of the word line 32b and the bit line 34f, the two bits b3 and b4 are used to validate only the extension 42b of the line of words while inhibiting the extensions 42a, 42c and 42d. The word line 32b is thus connected to the word output line 45. Similarly, the bit decoder 25, using the bits b0 and b1, excites the output of the NAND gate 40b which in turn excites the line. bit pre-decoder 3Gb while leaving the other lines 36a, 36c, and 36d inhibited. Thus, the bit line 34b is electrically connected to the pre-decoder output line 38a and the bit line 34f is simultaneously connected to the pre-decoder output line 38b. The bit b2 is then used to select only the output of the pre-decoder 26b so as to connect the output line 38b of the pre-decoder to the output 33 of the decoder 30. Consequently, if there is a diode present at the intersection of the word line 32b and the bit line 34f, a unidirectional flow of current will then be possible. Moreover, if no

  diode is present in the arrangement 12 at this inter-

  section, then no flow of current will be possible.

  The inhibited lines of words and bits 32a, 32c and 32d, and 34a, 34c, 34d, 34e, 34K and 34h respectively are all connected to Vdd by the deselectors 17, 27 to

  the way previously explained.

  In order to "read" the contents of the memory cell at the addressed location, an attempt is made to pass current through a diode that may be present, thereby attempting to pass current from the output line. from bit decoder 33 to the word decoder output line 45. Whether or not this attempt succeeds determines whether a "0" or a "1" will be read

of the addressed cell.

  As previously described, ROM 10 according to the invention comprises an x-y arrangement 12 which contains 2k memory cells. Each cell includes an intersection of a word line and a bit line

  o is selectively formed a buried contact diode.

  (when the ROM is "programmed") as previously described. In order to construct the ROM according to the preferred embodiment of the invention, it starts with an insulating substrate on which can be drawn a monocrystalline semiconductor material such as the sapphire substrate 60 of Figure 3. On the sapphire substrate 60, is epitaxially driven a layer 62 semiconductor

  monocrystalline silicon compound in the embodiment

  preferred embodiment of the invention. In the preferred embodiment of the invention, the silicon layer 60 has a

  surface parallel to the plane (100) of the crystallographic axis.

  Substrate 60, with the epitaxial silicon layer 62 on top, is placed in an oxidation furnace heated to about 1050 C for a time sufficient to draw an oxide layer 64 of a thickness of 1000 At the surface of the silicon layer 62. Then, a layer of "photoresist" or photoresist 66 is applied to the surface of the layer 64 of silicon dioxide. By using a first photomask, the layer 66 is defined photolithographically, in order to be able to use it to transform the silicon layer 62 into linecodes of the arrangement and sextensions of the bit lines that form part of the word and circuit pre-decoder circuit. previously described word line deselect. Then, the defined deuphotoresist layer 66 is developed and used as the etch mask to define the silicon dioxide layer 64. Typically, an etchant such as buffered hydrofluoric acid (HF) is used to remove the portions of the silicon dioxide layer 64 that are exposed through the etching mask, then the portions of the underlying silicon layer 62 that are exposed as a result of the etching of the layer 64 are removed by etching in a suitable attacking agent such as potassium hydroxide (KOH).

  of the silicon layer 62, the previous layer is used.

  etched silicon dioxide 64 as a mask,

  to thereby transform the layer 62 into islands.

  Then, the remaining parts of the layer 66 are torn off to give the silicon layer 62 the

  structure shown in Figure 4.

  The partially formed ROM is then covered with a second layer of "photoresist" material which is defined in a second photolithographic step using a second photomask. The "photoresist" layer is defined to expose all N0 type channel transistors, if present, while covering all h-type channel transistors. Acceptor ions, such as boron ions, are implanted in MOS transistors

  N-type channel to establish their thresholds.

  In the preferred embodiment of the invention, the acceptor ions are implanted at an energy threshold of the order of 70 KeV at a dose of the order of 10 ions per square centimeter. So, the second layer of "photoresist"

  is torn off, and all the substrate is subjected to an implan-

  non-selective determination of a donor ion such as phosphorus at an energy of about 70 KeV at a dose of about 10 ions per square centimeter in order to establish the threshold voltage of the P-channel MOS transistors Thereafter, all the oxide is removed from the partially formed ROM, which is then placed in an oxidation furnace heated to about 10,000 ° C. for a time sufficient to grow oxide layers 68 on a thickness of order of RJJA on the exposed silicon surfaces, as can be seen in FIG. 4. The layers 68 are illustrated on the epitaxial layers defined in silicon comprising the bit lines 34a-34h

  and the extensions of the word lines 42a, 52a.

  Referring now to FIG. 5, another layer of "photoresist 70 is applied to the surface of the wafer and a third photomask, referred to as the oversized buried contact mask" is used to define the layer 70. The defined layer 70 is used as an ion implantation mask which exposes oxide layers 68 in all areas where buried or embedded contacts may be formed. i.e. the entire surface of the memory arrangement 12. The oxide is then exposed on the intersections in the word line deselectors 17, the word pre-decoders 18, the bit pre-decoders 26 and bit line deselectors 27 o no type A channel MOS transistor is desired, i.e. intersections that are not represented by an "x" in Figure 2. Deep siting P + of acceptor ions, such as boron ions (represented by the arrows in FIG. 5) is then carried out at an energy of the order of 70 KeV at a dose of the order of 1013 ions per square centimeter across the oxide layers 68 in epitaxial silicon. The deep implantation of P + ions is used to give, to the lines of bits

  34a-34h, a conductivity of the P + type and to put into

  M-channel MOS transistors that would otherwise be formed in deselectors 17, 27 and pre-decoders 18, 26 at non-designated intersections

by xnx in Figure 2.

  Another layer of "photoresist" (not shown is then applied to the existing layer 70, and a fourth photomask, called the "programming mask" or the "buried contact mask" is used to selectively expose areas or surfaces of the layers When the oxide layer 68 is intersected in arrangement 12 and buried contact diodes are formed, the newly defined "photoresist" layer is then developed and used as a mask for removing exposed layers of wherein bit lines 68 are selected at the locations where these bit lines will be crossed by the word lines and where buried contact diodes, i.e., bit lines 34a, 34d, are desired. , 3 and 34h as will be seen in Figure 6. The two layers of "photoresist" on the pellet are then

withdrawn.

  Then, a layer 72 of polycrystalline silicon

  is deposited on a thickness of the order of 6500 A

  above the entire surface of the memory 10 partially formed by any suitable method. The layer 72 is doped to have N + type conductivity, typically using phosphorous oxychloride. As a result of the doping of the polycrystalline silicon layer 72, buried contact diodes are formed between the layer 72 and the bit lines 34a, 34d, 34p and 34b from which the oxide layers 68 have been removed as is represented in FIG. 6. Thus, the definition of the openings of the buried contacts by using the fourth photomask,

  is used to program the arrangement 12 of the ROM 10.

  The polycrystalline silicon layer 72 is then covered with a new layer of "photoresist"

  (not shown) used in a photolithographic step

  with a fifth photomask to define the polycrystalline silicon layer 72 into various lines of words and lines of pre-decoders. In addition, layer 72 is defined to form interconnects and gates

  of the logic circuit which is incorporated in the memory 10.

  The logic circuit comprises registers, selectors.

  stages of attack, and others as well as decoders and

pre-decoders described here.

  Following the definition of the polycrystalline silicon layer 72, as can be seen in FIG. 6, the source and drain regions of the P + type and the N + type of the various transistors in the memory 10 are formed using two additional photomasks and photolithographic steps followed by steps

ion implantation standards.

  Then, a field oxide layer 74 is deposited

  on the surface of partially formed ROM 10.

  Then, apertures 75 are photolithographically defined in field oxide 74 and apertures 75 are formed by etching. Then a layer of metal is applied to the surface of the ROM 10 partially

  completed and the metal layer is defined photolitho-

  graphically to form interconnects and the staggered metal contacts 44a, 50a, as can be seen in FIG. 7. Finally, a protective oxide layer 76 is deposited on the surface of all the ROM memory 10, and openings connecting pads (not shown)

  are formed there, thus completing the ROM 10.

  While the present invention has been described with reference to an SOS structure, those skilled in the art will recognize that a bulk or bulk silicon version of the ROM can easily be implemented by replacing the silicon lines. epitaxially diffused into a bulk silicon substrate. Given the fact that other aspects of

  the invention flow directly from the description of

  the invention relating to FIGS. 1 and 2, those which are

  competent authorities in this field will not need any explanations

  additional implementation of the ROM implementation

  according to the invention in a bulk silicon structure.

  While the preferred embodiment of the present invention has been described herein, those skilled in the art will recognize that many changes can be made to it. In particular, the ROM may be constructed in accordance with the present invention with the conductivity types of the various reversed semiconductor regions. Likewise, the number and arrangement of the memory cells in the x-y arrangement can be changed. Thus, while a 32 x 1 ROM design has been described, a 32K x 8 ROM using the present invention has been investigated by the present inventors. Likewise, other changes, such as replacing semiconductors with metals such as aluminum, or using Schottky diodes in the x-y arrangement are considered part of the scope of the invention. Thus, semiconductor word lines can be replaced by lines of metal words forming Schottky diodes in

  the x-y arrangement with half-bit lines

underlying driver.

  Of course, the invention is not limited to the embodiment described and shown which has been given by way of example. In particular, it includes all means constituting technical equivalents

  described means as well as their combinations if these

  These are executed according to his spirit and implemented

  as part of the protection as claimed.

Claims (4)

R E V E N D I C A T I 0 S   1. A device for electrically joining the ends of a first set of semiconductor lines substantially parallel to the adjacent ends of a second group of substantially parallel semiconductor lines and in equal numbers characterized by a number of contacts of metal (44a-44d), each of which covers the adjacent ends of a line of each of said goupes, said contacts (44a-44d) being staggered in the direction in which said parallel lines extend to allow said contacts (44a-44d) covering the ends of said lines while occupying the minimum space required in a direction substantially parallel to that in which said semiconductor lines substantially extend; 1 z parallels.   2. Disoositif according to claim 1 characterized in that the first group of substantially parallel lines (32a-32d) above comrrend a group of semiconductor lines monoc-fs'al! In and epitaxial   formed on an insulating substrate (60).   3. Device according to claim 2 characterized in that the aforementioned lines of the second group of substantially parallel semiconductor lines (42a-42d)   consist of polycrystalline silicon.   4. Device according to claim 3 characterized in that said metal contacts (44a-44d) are arranged in two rows which extend in a direction perpendicular to that in which extend said substantially parallel semiconductor lines V0 and in that adjacent metal contacts (44a-44d) are arranged in alternating rows, thus said contacts occupy the minimum space required in the direction in which said semiconductor lines extend. and substantially parallel.