FR2474741A1 - LINE SELECTOR FOR "STEP" DECODING OF MULTIPLE INPUT LINES - Google Patents

Abstract

The line selector includes a plurality of closely adjacent input lines (34a to 34h) and has means for decoding the input lines into at least one output line (38a, 38b), the effective spacing of which is coarser by any desired factor than the spacing of the input lines (34a to 34h). For decoding the input lines while making the output spacing coarser in relation to the input spacing, an arrangement of MOS transistors is provided in the line selector (26a, 26b).

Description

 The present invention relates to memories mtescu "ROM" on integrated circuit.

 ROMs or ROMs are used in electronic circuits to store information and perform logical functions. In particular, they are used in digital equipment, including minicomputers and microprocessors. In order to increase the economy of the manufacture of the ROMs and to reduce the size of the general systems employing them, it is advantageous to have the greatest possible number of memory bits per integrated circuit chip. Accordingly, it is desirable to decrease the area used for each storage cell, a storage cell being the part of the integrated circuit that stores a single bit of information. The storage cells are generally in an xy memory arrangement with a decoder circuit located along the x-axis of the arrangement for selecting a particular column of the storage cells and an additional decoder circuit located along the y-axis for selecting a particular row of cells so that the intersection of the decoded row and column gives a particular bit of information that can be accessed.

 The size of the cells in the memory arrangement determines the density of the cells in the x or y direction, i.e. how the rows and columns of the cells can be approximated. The interval is called the "step" of the arrangement. Note that the "pitch" of the rows may differ from the "pitch" of the columns depending on how the arrangement is implemented and the particular design rules that are used.

 In the present description, the term "design rules" indicates the rules that define the dimensions of the minimum width of a line and the minimum space between the lines that can be reliably obtained by the technology in use. .

 Until now, the ROMs were commonly implemented using a MOS transistor for each cell, the MOS transistor being set to either a conductive or non-conductive state. The arrangement of memory arrangements using such prior cells requires the presence of contact areas between a metal layer and an underlying line of epitaxial silicon.

Such metal-silicon contacts are added to the size of the memory arrangement, directly affecting the size of the chip. This was not previously a problem, because the ultimate limit on the rows and columns of cells in the arrangement was usually not determined by cell size but by the size of the decoding circuit placed adjacent to the cells. x and y edges of the arrangement;
It is desirable to keep the decoder circuit "in step" with the rows and columns of the arrangement for well-known reasons. Accordingly, it is desirable to reduce the size of the decoder circuit so that the decoders correspond to the pitch of the cells in the memory arrangement, thereby decreasing the ultimate size of the chip. Given that a decoder circuit requires a number of gates, and that each door requires a number of transistors, the pitch of the decoder circuit available Up to now was much higher than that at which the cells in the arrangement could between arranged. Thus, most of the efforts made to date in the development of ROMs concerned designs to reduce the space required by the decoder circuit.

 The present inventors have found a way to increase the effective pitch of memory cells.

This method can be used to substantially increase the effective pitch of the memory cells in the arrangement by a power of 2, a power of 4, a power of 8, and so on.

In addition, the present inventors have studied a new memory arrangement where the cells can occupy the minimum space allowed by the design rules in use. Thus, the combination of the new memory arrangement with the new method to increase the effective pitch of the cells in the arrangement, gives a ROM where the decoder circuit can be constructed of traditional devices, and yet the completed chip will have many more cells than memory that a
ROM built in a traditional way using the same surface of pellet.

 According to the invention, a memory arrangement and an associated decoding scheme will be described. The arrangement is comprised of a series of oxide-coated minimum width and parallel oxide epitaxial lines where the minimum space between adjacent lines permitted by the design rules is used. Covering the epitaxial silicon lines and being orthogonal thereto, there is a series of doped polycrystalline silicon lines which are parallel and of minimum width. The epitaxial silicon lines are all doped to have the same type of conductivity and the lines polycrystalline silicon are all doped to have the opposite type of conductivities The number of intersections, looking from above, polycrystalline silicon lines with epitaxial silicon lines will be the product of the number of epitaxial silicon lines n by the number of lines polycrystalline silicon, "m". Thus, there will be "n" times "m" intersections. At each intersection, an "embedded contact" diode may be formed by removing the oxide from the epitaxial silicon line before depositing over the polycrystalline silicon line. The memory arrangement therefore consists of a series intersections that can be selectively programmed to have either a diode or an open circuit between a given polycrystalline silicon line and the epitaxial-underlying silicon line. The arrangement therefore requires the minimum space allowed by the design rules for a maximum number of storage cells.

 In order to detect the presence or absence of a diode at a particular intersection, an attempt is made to pass the current through a selected polycrystalline silicon line and to detect this outgoing current through a selected epitaxial silicon line. If the attempt is successful, it means that a diode is present at the intersection.

On the other hand, if the attempt does not succeed, then there is no diode at this intersection. As will be apparent to those skilled in the art, the current flow attempt is made compatible with the polarity of buried or embedded contact diodes that may be present.

Design rules that require a minimum epitaxial silicon line width ("bit line" of 7>>, and a minimum gap between 4E lines, determine that the pitch of the columns of cells in the layout may As a result, a minimum width of a polycrystalline silicon line ("word line") of 3vlL with a minimum gap between the lines of 4 between the polycrystalline silicon lines determines that the pitch of the rows of cells in the layout can only reach 7
Given the fact that up to now there was no known way of constructing a decoder to correspond to a step of 7># rows, the high-density buried contact memory arrangement described here does not exist. could be useful in the manufacture of a high density ROM without the single multistage decoder circuit studied by the present inventors.

 The decoders in a ROM memory serve the function of selecting a particular bit in the memory arrangement. This is usually accomplished in the manner previously described. Typically, the total number of bits in a ROM is a factor of 2, so an individual bit can be chosen by specifying its address as a binary number. In particular, the total number of bits in the memory array, i.e., "n" times "m", is usually 2k, where k is the number of bits in the binary address available to specify the particular memory location that needs to be read.

Typically, "n" and "m" are also powers of 2.

So, if n equals 21, then m equals 2 (ki)
In order to select a particular location in the memory for reading in the arrangement, one of the two rows is selected, each having 2 (ki) columns. Then, one of the 2 (ki) columns is chosen to address the desired bit. A common method for selecting a desired bit is to have a line selector selecting one of the 2 lines of words and another line selector choosing one of the 2 (ki) bit lines. Thus, a selector of 1 of 2in lines is typically used as a word line decoder and a selector of 1 of 2 (ki) lines is typically used as a bit line decoder. "lines is generally implemented using NAND gates with i inputs and i inverters, there is no known way to make a selector 1 d 2i lines at a step of 7 t (for any given value of i ).

 It was particularly useful that the actual step of the memory arrangement could be a certain multiple of 7 / a-. According to the present invention, the effective pitch of the rows of cells in the arrangement can be an arbitrary factor of 2 multiplied by 7yt, ie 14 microns, 28 microns, 56 microns, etc. Given the fact that the present inventors can build a word decoder having a pitch of 28v2- with a final stage that converts the pitch of rows from 7 2t to a step of 28? while simultaneously producing an output to 1 of 4, it is possible to produce a memory chip having a very high cell density XauxqueIstrestrespondent an associated decoder circuit. Similarly, the effective pitch of the columns can be increased by any desired power of 2.

The invention will be better understood, and other objects, features, details and advantages thereof will appear more clearly in the following explanatory description made with reference to the accompanying schematic drawings given solely by way of example illustrating a embodiment of the invention and in which
FIG. 1 is a block diagram of the ROM according to the present invention;
FIG. 2 is a partial schematic and partly in plan view of the ROM, describing its memory arrangement and associated features; and
Figures 3 to 7 are cross-sectional views taken along line 3-3 of Figure 2, illustrating the manner in which the ROM is fabricated.

 Referring now to Figure 1, there can be seen a block diagram of the ROM 10 constructed according to the present invention. The ROM 10 consists of an x-y memory arrangement 12 of 2k memory cells, having word lines and 2 (k i) bit lines. In order to extract a single information bit from the arrangement 12, it is necessary to address both the bit line and the word line associated with a particular cell in the x-y arrangement 12. Accordingly, an address comprising k bits must be applied to an address register 14. From the register 14, two bits are extracted and placed on a word decoding line 16 and connected to a word address decoder 19. Decoder 19 is connected to a series of word pre-decoders 18. Each word pre-decoder according to the preferred embodiment of the invention is a selector of 1 of the 4 lines of a type which will be described hereinafter. Word pre-decoders or word line selectors 18 may be designed to produce a selection of the 4 lines in the previously indicated 28 / oc step, as will be better described below.

 From the address register 14, i-2 bits are applied by a word decoding line 20> to a word decoder 22.

The decoder 22 is a selector of 1 of2 (i-2) lines.

The decoder 22 has the function of choosing one of the predecoders 18. Each of the pre-decoders 18 of this particular embodiment is connected to 4 lines of words of the arrangement 12. Based on the 2 bits on the line 16, the word address decoder 19 forces each of the pre-decoders 18 to choose one of the 4 lines of words to which they are connected. The decoder 22 simultaneously chooses one of the word pre-decoders 18.

As a result, i bits are used to choose one of the word lines in arrangement 12 in xy.
Similarly, 2 bits of the address register 14 are applied, by a bit pre-decoding line 24, to a bit address decoder 25. The decoder 25 is connected to a series of bit pre-decoders 26 Each pre-decoder 26 is a selector of 1 of the 4 lines connected to 4 bit lines in the embodiment described. The remaining ki-2 bits in the register 14 are applied to a bit decode line 28 of the address register at the bit decoder 30 which is a selector of 1 of the 2 (ki-2) lines.

 Accordingly, k-i bits of the address are used to choose one of 2 (k-i) bit lines present in the arrangement 12.

 According to the above decoding description, k bits placed in the register 14 are used to choose one of the 2k memory cells present in the arrangement 12. The pre-decoders 18, 26 are intended to match the pitch decoders 22, 30 at the pitch of the arrangement 12 while simultaneously assisting the decoding process. As described above, the predecoders 18, 26 of this embodiment are selectors of one of the 4 lines. However, it will be obvious to those skilled in the art that predecoders 18, 26 may be selectors of one of the 8 lines or selectors of 1 of the 16 lines.

 Accordingly, pre-decoders 18, 26 which are 4-line selectors as described herein should be considered representative rather than exhaustive.

 Like the pre-decoders 18, 26, there are word line deselectors 17 and bit line deselectors 27, connected to the same lines of words and bit lines as the associated pre-decoders 18 (line selectors). words) and 26 (bit line selectors). The deselectors 17, 27 are intended to inhibit 3 of the 4 lines that are not connected to the memory cell that is addressed. The deselectors 17 are connected to the word decoding line 16 by a word line descrambler address decoder 29 and the bit line deselectors 27 are connected to the bit decoding line 24 by an address decoder. bit line deselector 31.

 Referring now to Figure 2, there is shown a top and partially schematic view of the ROM 10 built according to the present invention.

For simplicity of explanation, the memory arrangement 12 is an x-y arrangement having 4 word lines 32a = 32d and 8 bit lines 34a-34h. The preferred embodiment ROM is constructed using silicon-on-sapphire (SOS) technology, where an epitaxial silicon layer is drawn over an insulating substrate, typically sapphire. The bit lines 34a-34h consist of P + type epitaxial silicon, and the 32a-32d word lines consist of N + type polycrystalline silicon. When the arrangement 12 is constructed, the epitaxial silicon bit lines 34a-34h # are covered with an oxide layer. Typically, a layer of thermal silicon dioxide is drawn on the bit lines 34a-34h. The arrangement 12 is then programmed by removing the oxide, typically by etching into buffered hydrofluoric acid (HF), portions of bits lines 34a = 34h where intersections will be formed with the word lines 32a = 32d and where diodes are desired.

Thus, when the polycrystalline silicon word lines 32a-32d are deposited and defined on the epitaxial silicon bit lines 34a-34h, diodes are formed by contact between the word lines 32a-32d and the bit lines 34a-34b. 34h at particular intersections. The particular intersections where diodes are formed correspond to the data programmed in the ROM as will be obvious to those who are competent in the subject.

 The function of the ROM is to store the information in binary form. The ROM works by indicating the presence or absence of a diode when a particular memory address is chosen. As will also be apparent to those skilled in the art, the term "memory address n" denotes the binary code that identifies a particular intersection of a word line 32 and a bit line 34; to say a particular cell.

 Continuing to refer to Figure 2, the bit lines 34a-34h extend downward beyond the x-y memory arrangement 12 in the bit pre-decoders 26a, 26b. The address decoder 25 of the particular embodiment shown in FIG. 2 comprises, in part, four NAND gates 40a-40d that drive the pre-decoders 26a, 26b. The pre-decoders 26a, 26b consist of 4 polycrystalline silicon bit pre-decode lines 36a-36d which cover the bit lines 34a-34h. As described above, the lines 34a-34h consist of epitaxial silicon lines of the P + type. However below the intersections indicated by an "x", where a silicon bit pre-decoding line polycrystalline 36a-36d covers an epitaxial silicon bit line 34a-34h, the epitaxial silicon bit lines are doped to be of type NI conductivity, Accordingly, each bit pre-decoder 26a, 26b acts as a switch to a pole and four positions, if a negative potential is imposed on only one of the lines 36a-36d in a given time. For example, if the line 36a is maintained at a negative potential while the other lines 36b, 36c and 36d are maintained at the maximum positive potential of the chip, only the lines 34a and 34e will be connected to the outputs 38a, 38b of the pre-decoders , respectively.Thus, by appropriately exciting the bit pre-decoder lines 36a-36d, the pre-decoders 26a, 26b will each have a single output line 38a, 38b connected to the arrangement 12.

Given that the pre-decoders 26a, 26b can be formed with the same rules of geometry and design as the arrangement 12, the pre-decoders 26a, 26b can be built "in step" with the arrangement 12 of memory in xy. In the preferred embodiment of the invention, there is a 4 to 1 decrease in the effective pitch of the bit lines 34a-34h relative to the pitch of the output lines of the pre-decoders 38a, 38b. Similarly, one could obtain a reduction of 2 to I, a reduction of 8 to 1 or any other desired reduction using the bit predecoders according to the invention.

 When the bit pre-decoding has been completed, "out of step" decoding of the outputs 38a, 38b can be performed. In the present embodiment of the invention, it is assumed that no decoder can be constructed with a pitch four times greater than the pitch of the columns of arrangement 12. Accordingly, further decoding of output lines 38a, 38b can easily be accomplished with an effective reduction of the step from 4 to 1.

The decoder 25 consists of a series of doors
NAND with two inputs, 40a-40d, the outputs of which are connected to the pre-decoder lines 36a-36d, and two inverters 41a, 41b, the inputs and outputs of which are connected to the inputs of the NAND gates 40a-40d. 40d. The decoder 25 is used to appropriately energize the lines 36a-36b which form the transistor gates.
MOS where they cut the bit lines 34a-34h at the intersections designated by the "x". The decoder 25 requires two bits of the memory address, b0 and b1, to select one of the four pre-decoder lines 36a-36d.

 Following the reduction from 4 to 1 of the effective pitch of the bit lines 34a-34h to the effective pitch of the pre-decoder output lines 38a, 38b, the lines 38a, 38b can be decoded by a conventional circuit (indicated by the reference 30 in Figure 2). The decoder 30 has a single output line 33. As will be understood by those skilled in the art, the decoder 30 of the embodiment shown in FIG. 2 will require 1 bit of the memory address, b2, to select the one of the two output lines 38a, 38b and for connecting the selected output line to the output line 33 of the decoder.

 Referring now to the word decoding process of the embodiment shown in Fig. 2, those skilled in the art will recognize that it is desirable that the word decoding process be undertaken in a manner equivalent to the process of decoding. Bit decoding just described. However, the same type of decoding circuit can not be used because the bit lines 34a-34h of the arrangement 12 sc # t epitaxial silicon lines which are formed in the drain, source and channel regions of the transistors. isolated gate field effect in the bit pre-decoders 26a, 26b as previously explained. Moreover, the word lines are polycrystalline silicon lines which can not be used to form the drain, source and of insulated gate field effect transistor channel to form a word predecoder of the type used to decode the bit lines.

 In order to remedy this situation, and to use, for the word pre-decoding, a circuit equivalent to that used for the bit pre-decoding, word line extensions 42a-42d are formed of epitaxial silicon of the P + type. at the same step as the 32a-32d word lines.

Adjacent ends of extensions 42a-42d and word lines 32a-32d are electrically joined by staggered or staggered metal contacts 44a-44d.

The contacts 44a-44d are staggered to allow them to cover the width of the lines 32a-32d and the extensions 42a-42d while taking the minimum amount of space needed in the direction in which the word lines 32a-32d and the extensions 42a-42d extend. The staggered metal contacts 44a-44d thus form an ohmic contact, and yet they are not short-circuited with each other. Thus, the staggered metal contacts 44a-44d form a "pitch" connection between the polycrystalline silicon word lines 32a-32d and the extensions of the epitaxial silicon word lines 42a-42d, and they make it possible to implement a word pre-decoder in exactly the same way as the bit pre-decoders 26a, 26b have previously been implemented. Accordingly, the pre-decoder 18 uses the polycrystalline silicon lines 43a-43d in the same way as the bit decoders 26a-26b use the polycrystalline silicon lines 36a-36d. The predecoder 18 is functionally equivalent to the predecoders 26a, 26b so no further explanation will be given. In addition, since there are only four word lines, 32a-32b, in the present embodiment of the invention, the pre-decoder 18 performs all word decoding, so no additional decoder n1 is required.

 Note that two bits of the memory address, b3 and are used to decode the word lines, 32a-32d to choose one of them and connect it to the line output words 45. The decoder of necessary word address 19, which functions in the same way as the bit address decoder 25 explained above, is schematically shown in FIG. 2. Those skilled in the art will understand that the decoder circuit 19 may be identical to that of the decoder 25.

 Based on the foregoing description of the address scheme used to select a particular address in the arrangement 12, a 5 bit address is required to address the 32 memory cells in the arrangement 12. As those who are competent in this regard, it will be understood that the number of cells in arrangement 12 is equal to 32. Referring to FIGS. 1 and 2, it can be seen that in the embodiment described in FIG. 2, 2 bits are used. (bO and bl) of the 5-bit address for the pre-decoding of the bit line, 1 bit (b2) of the address for the decoding of the bit line and 2 bits of the address (b3 and b4) for the pre-decoding of the word line (which is also the decoding of the word line in this example). Thus, using the notation that was previously used, k is equal to 5, and i is equal to to 2 for the ROM described in Figure 2.

 it is undesirable to leave electrically "floating" lines because a floating line can pass to an unknown potential that may impair the proper functioning of the circuit. Accordingly, the bit lines 34a-34h extend upwardly of the arrangement 12 in the bit line deselector 27 which serves to connect the 3 of the 4 bit lines which are not selected. at a known and positive potential of the pellet.

 In the embodiment of the invention shown in Fig. 2, the de-selector 27 connects the unselected bit lines 34 to the highest positive potential of the chip, i.e. Vdd.

The descrambler 27 is similar to pre-decoders 26a, 26b because it consists of 4 polycrystalline silicon lines 46a-46d which overlap the bit lines 34a-34h. As previously described, the lines 34a-34h consist of epitaxial silicon lines of the P + type. However, below the intersections indicated by an "x" where one of the polycrystalline silicon descrambler lines 46a-46d overlaps one of the epitaxial silicon bit lines 34a-54h, the epitaxial silicon bit lines are doped to be of N-type conductivity to form P-type MOS transistors. As a result, the de-selector 27 acts as a four-position switch which connects three lines of each group of 4 bit lines to the positive potential. the highest of the pellet, ie Vdd. The 3 lines among the 4 bit lines that are connected to Vdd are the 3 lines that the pre-decoders 26a, 26b would otherwise have left floating.

The bit line deselector 27 is controlled by an address decoder 31. The decoder 31 of the preferred embodiment of the invention has a circuit similar to that of the bit decoder 25 except that the gates
NAND 40a-40d are replaced by NOR gates 54a 54b and inverters 39a, 39b are connected to give the NOR gates 54a-54d inverted inputs relative to the NAND gate entries 40a. -40d, respectively.

 Likewise, the word line despreader 17 in the embodiment of the invention shown in Fig. 2 connects the unspecified word lines to the highest positive potential of the chip, that is, to say Vdd. The deselector 17 is similar to the predecoder 18 because it consists of 4 polycrystalline silicon lines 48a-48d which cover the extensions of the word lines 52a-52d. As previously described, the word lines 32a-32d of the arrangement 12 consist of N + type polycrystalline silicon lines. As a result, the ends of the word lines 32a-32d are connected by staggered metal contacts 50a-50d to the P + 52a-52d-type epitaxial silicon word line extensions for the reasons explained above. Below the indicated intersections by an "xn", where one of the polycrystalline silicon de-commutator lines 48a-48d overlaps one of the extensions 52a-52d, the extensions are doped to be of N-type conductivity in order to form MOS channel-to-channel transistors. As a result, the de-selector 17 acts as a four-position switch which connects 3 lines of each group of 4 word lines to the highest positive potential of the chip, i.e. Vdd. lines of the 4 lines of words that are connected to Vdd are the 3 lines that the pre-decoder 18 would otherwise have left floating.

 The descrambler 17 is controlled by a word line descrambler address decoder 29. Those skilled in the art will recognize that the circuit for the decoder 29 of the preferred embodiment of the invention may be identical to that used for the bit line deselector address decoder 31. Similarly, the circuit used for the bit decoder 25 can also be used for the word address decoder 19 in this particular embodiment.

As a specific example, in order to address the memory cell placed at the intersection of the word line 32b and the bit line 34f, the two bits b3 and b4 are used to validate only the extension 42b of the line of words while inhibiting the extensions 42a, 42c and 42d. The word line 32b is thus connected to the word output line 45. Similarly, the bit decoder 25, using the bits b0 and b1, excites the output of the gate
NAND 40b which in turn energizes the bit pre-decoder line 36b while leaving the other lines 36a, 36c, and 36d inhibited. Thus, the bit line 34b is electrically connected to the pre-decoder output line 38a and the bit line 34f is simultaneously connected to the pre-decoder output line 38b. The bit b2 is then used to select only the output of the pre-decoder 26k so as to connect the output line 38b of the pre-decoder to the output 33 of the decoder 30. Consequently, if there is a diode present at the intersection of the word line 32b and of the bit line 34f, a unidirectional flow of current will then be possible. On the other hand, if no diode is present in the arrangement 12 at this intersection, then no flow of current will be possible.

 The inhibited lines of words and bits 32a, 32c and 32d, and 34a, 34c, 34d, 34e, 34g and 34h respectively are all connected to Vdd by the deselectors 17, 27 in the manner previously explained.

 In order to "read" the contents of the memory cell at the addressed location, an attempt is made to pass current through a diode that may be present, thereby attempting to pass current from the output line of the bit decoder 3 at the word decoder output line 45. The success or failure of this attempt determines whether an "o" or "1" will be read from the addressed cell.

 As previously described, ROM 10 according to the invention comprises an x-y arrangement 12 which contains 2k memory cells. Each cell includes an intersection of a word line and a bit line where a buried contact diode is selectively formed.

(when the ROM is "programmed") as previously described.

 In order to construct the ROM according to the preferred embodiment of the invention, it starts with an insulating substrate on which can be drawn a monocrystalline semiconductor material such as the sapphire substrate 60 of Figure 3. On the sapphire substrate 60, is epitaxially grown a monocrystalline semiconductor layer 62 made of silicon in the preferred embodiment of the invention. In the preferred embodiment of the invention, the silicon layer 60 has a surface parallel to the plane (100) of the crystallographic axis.

 Substrate 60, with the epitaxial silicon layer 62 over it, is placed in an oxidation furnace heated to about 10500C for a time sufficient to draw an oxide layer 64 having a thickness of 1000 A. on the surface of the silicon layer 62. Then, a "photoresist" or photoresist layer 66 is applied to the surface of the silicon dioxide layer 64. Using a first photomask, the layer 66 is defined photolithographically, in order to be able to use it to transform the silicon layer 62 into a bit line of the arrangement and # extensions of the bit lines that form part of the word pre-decoder circuit and Thus, the defined "photoresist" layer 66 is developed and used as the etch mask to define the silicon dioxide layer 64. Typically, an etchant such as buffered hydrofluoric acid (HF) is used to remove the portions of the silicon dioxide layer 64 that are exposed through the etch mask. Then, the portions of the underlying silicon layer 62 which are exposed as a result of the etching of the layer 64 are etched away in a suitable etchant such as potassium hydroxide (KOH). In etching the exposed portions of the silicon layer 62, the previously etched layer of silicon dioxide 64 is used as a mask, thereby transforming the layer 62 into burps.

 Then, the remaining portions of the layer 66 are torn off to give the silicon layer 62 the structure shown in FIG.

 The partially formed ROM is then covered with a second layer of "photoresist" material which is defined in a second photolithographic step using a second photomask. The "photcresist" layer is defined to expose all Ns-type channel transistors if present while covering all Bt-type channel transistors. Acceptor ions, such as boron ions, are implanted in the transistors. MOS to Nlafin type channel to establish threshold urstensions.

In the preferred embodiment of the invention, the acceptor ions are implanted at an energy threshold of the order of 70 KeV at a dose of the order of 13 ions per square centimeter. Then, the second layer of "photoresist" is torn off, and all the substrate is subjected to non-selective implantation of a donor ion such as phosphorus, at a twist energy of 70 KeV at a dose of about 10 ions per square centimeter to establish the threshold voltage of the P-channel MOS transistors.

Then, any oxide is removed from the partially formed ROM, which is then placed in an oxidation furnace heated to about 1000 ° C for a time sufficient to flush oxide layers 68 on
Q a thickness of the order of SDA on the exposed silicon surfaces, as can be seen in Figure 4. The layers 68 are illustrated on the epitaxial layers
defined in silicon comprising bit lines 34a-34h and extensions of word lines 42a, 52a.

 Referring now to FIG. 5, another photoresist layer "70 is applied to the surface of the wafer and a third photomask, referred to as the oversized buried contact patch" is used to define the layer 70. The defined layer 70 is used as an ion implantation mask which exposes the oxide layers 68 in all areas where buried or embedded contacts may be formed, i.e. the entire surface of the memory arrangement 12.Oxide is then exposed to the intersections in the word line deselectors 17, the word pre-decoders 18, the bit pre-decoders 26 and the bit line deselectors 27 where no ~ type MOS transistor is desired, i.e. intersections that are not represented by an "xt" in FIG. 2. Deep implantation P + of acceptor ions, such as boron ions (represented by the arrows in FIG. 5) is then performed at a of about 70 KeV at a dose of the order of 1013 ions per square centimeter through the oxide layers 68 in the epitaxial silicon. The deep P + ion implantation serves to give, to the lines of bits 34a-34h, a conductivity of the P + type and short-circuiting the P-channel MOS transistors that would otherwise be formed in the deselectors 17, 27 and the pre-decoders 18, 26 at the intersections not designated by "x" on Figure 2.

 Another layer of "photoresist" (not shown) is then applied to the existing layer 70, and a fourth photomask, called the "programming mask" or "buried contact mask" is used to selectively expose areas or surfaces of oxide layers 68 where there will be intersections in the arrangement 12 and where buried contact diodes will be formed. The newly defined "photoresist" layer is then developed and used as a mask to remove exposed layers of 68 of the bit lines 34 selected at the locations where these bit lines will be crossed by the word lines and where buried contact diodes, i.e., bit lines 34a, 34 are desired. d, 34g and 34h as will be seen in Figure 6. The two layers of '1photoresist' on the pellet are then removed.

 Then, a layer 72 of polycrystalline silicon is deposited on a thickness of about 6500 A above the entire surface of the partially formed memory 10 by any suitable method. The layer 72 is doped to have N + type conductivity, typically using phosphorous oxychloride. As a result of the doping of the polycrystalline silicon layer 72, buried contact diodes are formed between the layer 72 and the bit lines 34a, 34d, 34g and 34h from which the oxide layers 68 have been removed as is Thus, the definition of the openings of the buried contacts using the fourth photomask, is used to program the arrangement 12 of the ROM 10.

 The polycrystalline silicon layer 72 is then covered with a new layer of "photoresist" (not shown) used in a photolithographic step with a fifth photomask to define the polycrystalline silicon layer 72 in various lines of words and lines of pre-decoders. . In addition, the layer 72 is defined to form interconnections and gates of the logic circuit which is incorporated in the memory 10.

The logic circuit includes the registers, selectors, driver stages, and the like, as well as the decoders and pre-decoders described herein.

 Following the definition of the polycrystalline silicon layer 72, as can be seen in FIG. 6, the source and drain regions of the P + type and the N + type of the various transistors in the memory 10 are formed using two additional photomasks and photolithographic steps followed by standard steps of ion implantation.

 Then, a field oxide layer 74 is deposited on the surface of the partially formed ROM 10.

Then, apertures 75 are photolithographically defined in field oxide 74 and apertures 75 are formed by etching. Next, a metal layer is applied to the surface of the partially completed ROM 10 and the metal layer is photolithographically defined to form interconnects and staggered metal contacts 44a, 50a, as can be seen in FIG. 7. Finally, a protective oxide layer 76 is deposited on the surface of the entire ROM 10, and bonding plug openings (not shown) are formed therein, thereby completing the ROM 10.

 While the present invention has been described with reference to an SOS structure, those skilled in the art will recognize that a bulk or bulk silicon version of the ROM can easily be implemented by replacing the silicon lines. epitaxially diffused into a bulk silicon substrate. In view of the fact that the other aspects of the invention flow directly from the description of the invention relating to FIGS. 1 and 2, those skilled in the art will not need any further explanation of the mode of implementation of the invention. of the ROM according to the invention in a bulk silicon structure.

 While the preferred embodiment of the present invention has been described herein, those skilled in the art will recognize that many changes can be made to it. In particular, the ROM may be constructed in accordance with the present invention with the conductivity types of the various reversed semiconductor regions. Likewise, the number and arrangement of the memory cells in the x-y arrangement can be changed. Thus, while a design of 32 x I ROM memory has been described, a 32K x 8 ROM using the present invention has been investigated by the present inventors. Likewise, other changes, such as replacing semiconductors with metals such as aluminum, or using Schottky diodes in the x-y arrangement are considered part of the scope of the invention. Thus, the semiconductor word lines can be replaced by metal word lines forming Schottky diodes in the x-y arrangement with underlying semiconductor bit lines.

 Of course, the invention is not limited to the embodiment described and shown which has been given as an example. In particular, it includes all means constituting technical equivalents of the means described and their combinations if they are executed according to its spirit and implemented in the context of the protection as claimed.

Claims (8)

 1.- Line selector, characterized by  (a) a first quantity of substantially parallel input lines (34a-34h) of a first conductivity type which enter said selector from a first side to a first pitch;  (b) a second quantity of substantially parallel conductive lines (36a-36d) that are substantially perpendicular to said input lines, said lines (36a-36d) intersecting said input lines (34a-34h) over and separated said input lines being insulators (68) at each intersection where one of said second lines (36a-36d) crosses one of said input lines (34a-34h);  (c) a single MOS transistor formed in each of said input lines (34a-34h) by inverting the conductivity type of each of said input lines below one of said substantially parallel lines (36a-36d), the only one said lines being the gate of said MOS transistor; and  (d) at least one output line (38a or 38b) composed of the junction of at least two of said input lines (34a-34h) of the side of said MOS transistor opposite the ctté where said input lines (34a-34b) 34h) enter said selector, whereby said selector can receive said input lines (34a-34h) from one side to said first step and select particular input lines for electrical connection to said output line (38a, 38b) by appropriate biasing of said conductive lines (36a, 36b), so only selected MOS transistors are turned on to thereby decode said input lines (34a-34h) for connection to said output line (38a, 38b) while simultaneously increasing the effective pitch of said decoded input lines (34a-34h).  2. Selector according to claim 1, characterized in that the input lines (34a-34h) above are formed of silicon.  3. A selector according to claim 2, characterized in that the input lines (34a-34h) above are formed of silicon epitaxially grown on an insulating substrate (60).  4. Selector according to claim 3, characterized in that the second lines (36a-36d) above are formed of polycrystalline silicon and doped.  5. A selector according to claim 3, characterized in that the insulators (68) above are formed of silicon dioxide regions which cover the first quantity of lines (34a-34h) above  6. A selector according to claim 2, characterized in that the second amount of lines (36a-36d) above is composed of metal.  7. A selector according to claim 6, characterized in that the aforementioned metal is alumina.  8. A selector according to claim 2, characterized in that the number of input lines (34a34h) above exceeds the number of conductive lines (36a-36d) above and in that the number of output lines (38a, 38b ) is less than or equal to the number of input lines (34a-34h) divided by the number of conductive lines (36a-36d).