FR2456435B1 - Circuit generateur de signaux de synchronisation, a lignes a retard - Google Patents
Circuit generateur de signaux de synchronisation, a lignes a retardInfo
- Publication number
- FR2456435B1 FR2456435B1 FR8010075A FR8010075A FR2456435B1 FR 2456435 B1 FR2456435 B1 FR 2456435B1 FR 8010075 A FR8010075 A FR 8010075A FR 8010075 A FR8010075 A FR 8010075A FR 2456435 B1 FR2456435 B1 FR 2456435B1
- Authority
- FR
- France
- Prior art keywords
- signal generator
- synchronization signal
- generator circuit
- delay lines
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/30—Time-delay networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/036,632 US4302735A (en) | 1979-05-07 | 1979-05-07 | Delay line compensation network |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2456435A1 FR2456435A1 (fr) | 1980-12-05 |
FR2456435B1 true FR2456435B1 (fr) | 1985-11-15 |
Family
ID=21889717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8010075A Expired FR2456435B1 (fr) | 1979-05-07 | 1980-05-06 | Circuit generateur de signaux de synchronisation, a lignes a retard |
Country Status (7)
Country | Link |
---|---|
US (1) | US4302735A (fr) |
JP (1) | JPS55153018A (fr) |
AU (1) | AU525883B2 (fr) |
CA (1) | CA1141439A (fr) |
DE (1) | DE3016819C2 (fr) |
FR (1) | FR2456435B1 (fr) |
GB (1) | GB2049334B (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2138230B (en) * | 1983-04-12 | 1986-12-03 | Sony Corp | Dynamic random access memory arrangements |
US4546269A (en) * | 1983-12-01 | 1985-10-08 | Control Data Corporation | Method and apparatus for optimally tuning clock signals for digital computers |
JPH0673524B2 (ja) * | 1984-01-18 | 1994-09-21 | 株式会社東芝 | 超音波診断装置用遅延回路 |
GB2187005B (en) * | 1986-02-21 | 1990-07-18 | Cirrus Designs Limited | Timing system for a circuit tester |
JP3461542B2 (ja) * | 1993-09-20 | 2003-10-27 | 富士通株式会社 | クロック分配装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB614720A (en) * | 1946-07-22 | 1948-12-22 | Gen Electric Co Ltd | Improvements in and relating to electric filter circuits |
US2931982A (en) * | 1950-10-26 | 1960-04-05 | Philips Corp | Device for converting pn-cycles pulse code modulation into pulse position modulation |
US3215942A (en) * | 1961-02-01 | 1965-11-02 | Hazeltine Research Inc | Compact pump signal supply circuit for traveling-wave parametric amplifiers |
US3660786A (en) * | 1970-08-20 | 1972-05-02 | Sprague Electric Co | Compensated delay line |
US4105978A (en) * | 1976-08-02 | 1978-08-08 | Honeywell Information Systems Inc. | Stretch and stall clock |
US4185323A (en) * | 1978-07-20 | 1980-01-22 | Honeywell Information Systems Inc. | Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations |
-
1979
- 1979-05-07 US US06/036,632 patent/US4302735A/en not_active Expired - Lifetime
-
1980
- 1980-04-16 CA CA000349989A patent/CA1141439A/fr not_active Expired
- 1980-05-01 AU AU57976/80A patent/AU525883B2/en not_active Ceased
- 1980-05-02 DE DE3016819A patent/DE3016819C2/de not_active Expired
- 1980-05-06 FR FR8010075A patent/FR2456435B1/fr not_active Expired
- 1980-05-07 JP JP6047880A patent/JPS55153018A/ja active Granted
- 1980-05-07 GB GB8015120A patent/GB2049334B/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
AU525883B2 (en) | 1982-12-02 |
DE3016819C2 (de) | 1984-12-20 |
DE3016819A1 (de) | 1980-11-20 |
JPS55153018A (en) | 1980-11-28 |
GB2049334A (en) | 1980-12-17 |
CA1141439A (fr) | 1983-02-15 |
AU5797680A (en) | 1980-11-13 |
JPS6116087B2 (fr) | 1986-04-28 |
US4302735A (en) | 1981-11-24 |
GB2049334B (en) | 1983-01-26 |
FR2456435A1 (fr) | 1980-12-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |