FR2400725A1 - Electronic digital clock with display corrector - has zero reset facility for display of cascaded dividing circuit output - Google Patents
Electronic digital clock with display corrector - has zero reset facility for display of cascaded dividing circuit outputInfo
- Publication number
- FR2400725A1 FR2400725A1 FR7725134A FR7725134A FR2400725A1 FR 2400725 A1 FR2400725 A1 FR 2400725A1 FR 7725134 A FR7725134 A FR 7725134A FR 7725134 A FR7725134 A FR 7725134A FR 2400725 A1 FR2400725 A1 FR 2400725A1
- Authority
- FR
- France
- Prior art keywords
- display
- cascaded
- electronic digital
- circuit output
- dividing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G5/00—Setting, i.e. correcting or changing, the time-indication
- G04G5/04—Setting, i.e. correcting or changing, the time-indication by setting each of the displayed values, e.g. date, hour, independently
- G04G5/043—Setting, i.e. correcting or changing, the time-indication by setting each of the displayed values, e.g. date, hour, independently using commutating devices for selecting the value, e.g. hours, minutes, seconds, to be corrected
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G5/00—Setting, i.e. correcting or changing, the time-indication
- G04G5/04—Setting, i.e. correcting or changing, the time-indication by setting each of the displayed values, e.g. date, hour, independently
- G04G5/041—Correction of the minutes counter in function of the seconds' counter position at zero adjustment of the latter
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
Abstract
The electronic digital clock has a control for correcting the displayed time on digital number displays (34-39). The clock comprises a high frequency reference oscillator (21) the output of which is fed through a cascaded dividing network (22 to 27). Outputs from each of the dividers represent hours, minutes, seconds etc. A control input (41) enables the display to be reset to zero whenever it is desired to correct the displayed time on the clock.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7725134A FR2400725A1 (en) | 1977-08-17 | 1977-08-17 | Electronic digital clock with display corrector - has zero reset facility for display of cascaded dividing circuit output |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7725134A FR2400725A1 (en) | 1977-08-17 | 1977-08-17 | Electronic digital clock with display corrector - has zero reset facility for display of cascaded dividing circuit output |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2400725A1 true FR2400725A1 (en) | 1979-03-16 |
FR2400725B1 FR2400725B1 (en) | 1982-01-15 |
Family
ID=9194562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7725134A Granted FR2400725A1 (en) | 1977-08-17 | 1977-08-17 | Electronic digital clock with display corrector - has zero reset facility for display of cascaded dividing circuit output |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2400725A1 (en) |
-
1977
- 1977-08-17 FR FR7725134A patent/FR2400725A1/en active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2400725B1 (en) | 1982-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |