FR2383483A1 - MEMORY ACCESS CONTROL CIRCUIT - Google Patents

MEMORY ACCESS CONTROL CIRCUIT

Info

Publication number
FR2383483A1
FR2383483A1 FR7806616A FR7806616A FR2383483A1 FR 2383483 A1 FR2383483 A1 FR 2383483A1 FR 7806616 A FR7806616 A FR 7806616A FR 7806616 A FR7806616 A FR 7806616A FR 2383483 A1 FR2383483 A1 FR 2383483A1
Authority
FR
France
Prior art keywords
memory
address
control circuit
access control
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR7806616A
Other languages
French (fr)
Inventor
Dietrich Illi
Hermann-Josef Golbach
Claus-Jurgen Becherer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of FR2383483A1 publication Critical patent/FR2383483A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention concerne un circuit de commande d'accès à la mémoire d'un microprocesseur. La mémoire de programme PS fournit une macro-instruction Mb qui peut être à adressage direct ou relatif au décodeur BD. Si l'adressage est direct, dA est transférée directement à l'entrée de la mémoire DS. Si l'adressage est relatif, l'adresse relative rA est envoyée dans l'additionneur Add avec l'adresse de la base bd après que celle-ci ait été extraite de la mémoire de bases BS due à l'application de l'adresse bsA. L'adresse effective eA est ainsi introduite AE dans la mémoire DS. L'invention trouve une application dans les systèmes de télécommunication commandés par calculateur.The invention relates to a circuit for controlling access to the memory of a microprocessor. The program memory PS provides a macro-instruction Mb which can be addressed directly or relating to the decoder BD. If the addressing is direct, dA is transferred directly to the DS memory input. If the addressing is relative, the relative address rA is sent to the adder Add with the address of the base bd after this has been extracted from the base memory BS due to the application of the address bsA. The effective address eA is thus entered AE in the memory DS. The invention finds application in computer-controlled telecommunications systems.

FR7806616A 1977-03-11 1978-03-08 MEMORY ACCESS CONTROL CIRCUIT Pending FR2383483A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772710671 DE2710671A1 (en) 1977-03-11 1977-03-11 CIRCUIT ARRANGEMENT FOR A MICROPROCESSOR TO CONTROL THE DATA STORAGE ACCESS

Publications (1)

Publication Number Publication Date
FR2383483A1 true FR2383483A1 (en) 1978-10-06

Family

ID=6003387

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7806616A Pending FR2383483A1 (en) 1977-03-11 1978-03-08 MEMORY ACCESS CONTROL CIRCUIT

Country Status (4)

Country Link
AU (1) AU3402278A (en)
DE (1) DE2710671A1 (en)
FR (1) FR2383483A1 (en)
GB (1) GB1567445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551931A2 (en) * 1987-06-05 1993-07-21 Mitsubishi Denki Kabushiki Kaisha Digital signal processor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3016952C2 (en) * 1980-05-02 1984-04-26 Standard Elektrik Lorenz Ag, 7000 Stuttgart Circuit arrangement for expanding the address range of a computer-controlled switching system
GB2307569B (en) * 1995-11-22 1998-06-10 Holtek Microelectronics Inc A method of indirect addressing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1252835A (en) * 1959-12-24 1961-02-03 Vickers Electrical Co Ltd Digital calculator
US3818460A (en) * 1972-12-29 1974-06-18 Honeywell Inf Systems Extended main memory addressing apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1252835A (en) * 1959-12-24 1961-02-03 Vickers Electrical Co Ltd Digital calculator
US3818460A (en) * 1972-12-29 1974-06-18 Honeywell Inf Systems Extended main memory addressing apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/68 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551931A2 (en) * 1987-06-05 1993-07-21 Mitsubishi Denki Kabushiki Kaisha Digital signal processor
EP0551931A3 (en) * 1987-06-05 1993-12-15 Mitsubishi Electric Corp Digital signal processor

Also Published As

Publication number Publication date
GB1567445A (en) 1980-05-14
DE2710671A1 (en) 1978-09-14
AU3402278A (en) 1979-09-13

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