FR2382098A1 - Procede pour faire des lignes etroites de silicium et dispositifs semi-conducteurs faits avec ces lignes - Google Patents

Procede pour faire des lignes etroites de silicium et dispositifs semi-conducteurs faits avec ces lignes

Info

Publication number
FR2382098A1
FR2382098A1 FR7805397A FR7805397A FR2382098A1 FR 2382098 A1 FR2382098 A1 FR 2382098A1 FR 7805397 A FR7805397 A FR 7805397A FR 7805397 A FR7805397 A FR 7805397A FR 2382098 A1 FR2382098 A1 FR 2382098A1
Authority
FR
France
Prior art keywords
lines
layer
semiconductor devices
devices made
making narrow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7805397A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of FR2382098A1 publication Critical patent/FR2382098A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H01L29/6678—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates on sapphire substrates, e.g. SOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur. Selon l'invention on forme une couche 10 en silicium polycristallin ayant un bord exposé et une couche 14 formant masque sur la couche 10, qui s'étend au moins jusqu'au bord exposé; on enfouit un dopant 18 du type P dans le bord exposé de la couche 10, sur une distance souhaitée latéralement le long de la couche 10; on enlève la couche 14 formant masque; et on enlève la partie non dopée de la couche 10. L'invention s'applique notamment à la préparation de transistors MOS à porte étroite.
FR7805397A 1977-02-28 1978-02-24 Procede pour faire des lignes etroites de silicium et dispositifs semi-conducteurs faits avec ces lignes Withdrawn FR2382098A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB826477 1977-02-28

Publications (1)

Publication Number Publication Date
FR2382098A1 true FR2382098A1 (fr) 1978-09-22

Family

ID=9849161

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7805397A Withdrawn FR2382098A1 (fr) 1977-02-28 1978-02-24 Procede pour faire des lignes etroites de silicium et dispositifs semi-conducteurs faits avec ces lignes

Country Status (5)

Country Link
US (1) US4271422A (fr)
JP (1) JPS53107287A (fr)
DE (1) DE2807138A1 (fr)
FR (1) FR2382098A1 (fr)
SE (1) SE7800261L (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2475293A1 (fr) * 1980-02-04 1981-08-07 Fairchild Camera Instr Co Procede de fabrication de transistor bipolaire lateral auto-aligne

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4312680A (en) * 1980-03-31 1982-01-26 Rca Corporation Method of manufacturing submicron channel transistors
US4684967A (en) * 1984-05-04 1987-08-04 Integrated Logic Systems, Inc. Low capacitance transistor cell element and transistor array
JP2653099B2 (ja) * 1988-05-17 1997-09-10 セイコーエプソン株式会社 アクティブマトリクスパネル，投写型表示装置及びビューファインダー
US5274279A (en) * 1988-05-17 1993-12-28 Seiko Epson Corporation Thin film CMOS inverter
US6413805B1 (en) 1993-03-12 2002-07-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device forming method
JPH06349735A (ja) 1993-06-12 1994-12-22 Semiconductor Energy Lab Co Ltd 半導体装置
US5985704A (en) * 1993-07-27 1999-11-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
JP3645380B2 (ja) 1996-01-19 2005-05-11 株式会社半導体エネルギー研究所 半導体装置の作製方法、情報端末、ヘッドマウントディスプレイ、ナビゲーションシステム、携帯電話、ビデオカメラ、投射型表示装置
US5985740A (en) 1996-01-19 1999-11-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device including reduction of a catalyst
JP3645379B2 (ja) * 1996-01-19 2005-05-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP3645378B2 (ja) 1996-01-19 2005-05-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6478263B1 (en) 1997-01-17 2002-11-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
JP3729955B2 (ja) 1996-01-19 2005-12-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5888858A (en) 1996-01-20 1999-03-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US6180439B1 (en) 1996-01-26 2001-01-30 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device
US7056381B1 (en) 1996-01-26 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of semiconductor device
US6465287B1 (en) 1996-01-27 2002-10-15 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device using a metal catalyst and high temperature crystallization
US6100562A (en) 1996-03-17 2000-08-08 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3890632A (en) * 1973-12-03 1975-06-17 Rca Corp Stabilized semiconductor devices and method of making same
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2475293A1 (fr) * 1980-02-04 1981-08-07 Fairchild Camera Instr Co Procede de fabrication de transistor bipolaire lateral auto-aligne

Also Published As

Publication number Publication date
DE2807138A1 (de) 1978-08-31
SE7800261L (sv) 1978-08-29
JPS53107287A (en) 1978-09-19
US4271422A (en) 1981-06-02

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