FR2375718A1 - High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components - Google Patents

High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components

Info

Publication number
FR2375718A1
FR2375718A1 FR7639159A FR7639159A FR2375718A1 FR 2375718 A1 FR2375718 A1 FR 2375718A1 FR 7639159 A FR7639159 A FR 7639159A FR 7639159 A FR7639159 A FR 7639159A FR 2375718 A1 FR2375718 A1 FR 2375718A1
Authority
FR
France
Prior art keywords
layers
high density
damage
minimises
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7639159A
Other languages
French (fr)
Other versions
FR2375718B1 (en
Inventor
Jean-Pierre Rioult
Jacques Journeau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Radiotechnique Compelec RTC SA
Original Assignee
Radiotechnique Compelec RTC SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Radiotechnique Compelec RTC SA filed Critical Radiotechnique Compelec RTC SA
Priority to FR7639159A priority Critical patent/FR2375718A1/en
Publication of FR2375718A1 publication Critical patent/FR2375718A1/en
Application granted granted Critical
Publication of FR2375718B1 publication Critical patent/FR2375718B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high density semiconductor and conducting layer matrix (1) is used, where interconnections are made between overlying layers. The design minimises problems of fabricating such devices and allows positional tolerances and engraving times to be reduced during the various masking operations. Undercutting and general damage to the various conducting layers is avoided by choice of suitable material dimensions and the use of etching resistant materials such that layers of silicon and silicon nitride overlap each other. Isolating materials used are silicon oxide and silicon nitride alternating with layers of an aluminium-silicon alloy and a titanium-tungsten alloy, the overlying layer being aluminium.
FR7639159A 1976-12-27 1976-12-27 High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components Granted FR2375718A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7639159A FR2375718A1 (en) 1976-12-27 1976-12-27 High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7639159A FR2375718A1 (en) 1976-12-27 1976-12-27 High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components

Publications (2)

Publication Number Publication Date
FR2375718A1 true FR2375718A1 (en) 1978-07-21
FR2375718B1 FR2375718B1 (en) 1979-04-20

Family

ID=9181562

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7639159A Granted FR2375718A1 (en) 1976-12-27 1976-12-27 High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components

Country Status (1)

Country Link
FR (1) FR2375718A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019883A2 (en) * 1979-05-24 1980-12-10 Kabushiki Kaisha Toshiba Semiconductor device comprising a bonding pad

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering
FR2219527A1 (en) * 1973-02-28 1974-09-20 Philips Nv

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2219527A1 (en) * 1973-02-28 1974-09-20 Philips Nv
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019883A2 (en) * 1979-05-24 1980-12-10 Kabushiki Kaisha Toshiba Semiconductor device comprising a bonding pad
EP0019883A3 (en) * 1979-05-24 1983-07-13 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device comprising a bonding pad

Also Published As

Publication number Publication date
FR2375718B1 (en) 1979-04-20

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Legal Events

Date Code Title Description
ST Notification of lapse