FR2375662A1 - Systeme asymetrique a processeurs multiples - Google Patents

Systeme asymetrique a processeurs multiples

Info

Publication number
FR2375662A1
FR2375662A1 FR7735660A FR7735660A FR2375662A1 FR 2375662 A1 FR2375662 A1 FR 2375662A1 FR 7735660 A FR7735660 A FR 7735660A FR 7735660 A FR7735660 A FR 7735660A FR 2375662 A1 FR2375662 A1 FR 2375662A1
Authority
FR
France
Prior art keywords
control
processor
macroprocessor
asymmetrical system
executing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7735660A
Other languages
English (en)
Other versions
FR2375662B1 (fr
Inventor
Ronald E Bodner
Richard C Kiscaden
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2375662A1 publication Critical patent/FR2375662A1/fr
Application granted granted Critical
Publication of FR2375662B1 publication Critical patent/FR2375662B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Abstract

Il comporte au moins un macroprocesseur 10 exécutant des instructions en langage système contenues dans la mémoire principale 15 sous le contrôle d'un processeur de contrôle 300 exécutant les micro-instructions d'une mémoire de contrôle 305. Le processeur de contrôle initie en outre le fonctionnement du macroprocesseur et traite les conditions d'interruption. L'invention permet de reduire les ressources, les interférences et les opérations de contrôle du système.
FR7735660A 1976-12-27 1977-11-18 Systeme asymetrique a processeurs multiples Granted FR2375662A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/754,390 US4077060A (en) 1976-12-27 1976-12-27 Asymmetrical multiprocessor system

Publications (2)

Publication Number Publication Date
FR2375662A1 true FR2375662A1 (fr) 1978-07-21
FR2375662B1 FR2375662B1 (fr) 1980-12-19

Family

ID=25034587

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7735660A Granted FR2375662A1 (fr) 1976-12-27 1977-11-18 Systeme asymetrique a processeurs multiples

Country Status (6)

Country Link
US (1) US4077060A (fr)
JP (1) JPS5382241A (fr)
DE (1) DE2755616C2 (fr)
FR (1) FR2375662A1 (fr)
GB (1) GB1589179A (fr)
IT (1) IT1126217B (fr)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4247893A (en) * 1977-01-03 1981-01-27 Motorola, Inc. Memory interface device with processing capability
US4128876A (en) * 1977-04-28 1978-12-05 International Business Machines Corporation Synchronous microcode generated interface for system of microcoded data processors
US4199811A (en) * 1977-09-02 1980-04-22 Sperry Corporation Microprogrammable computer utilizing concurrently operating processors
JPS54114687A (en) * 1978-02-27 1979-09-06 Toyoda Mach Works Ltd Sequence controller
JPS55500197A (fr) * 1978-04-21 1980-04-03
US4396981A (en) * 1978-10-02 1983-08-02 Honeywell Information Systems Inc. Control store apparatus having dual mode operation handling mechanism
US4545013A (en) * 1979-01-29 1985-10-01 Infinet Inc. Enhanced communications network testing and control system
WO1980001615A1 (fr) * 1979-01-29 1980-08-07 Intertel Inc Systeme ameliore de commande et d'essai d'un reseau de communication
US4310879A (en) * 1979-03-08 1982-01-12 Pandeya Arun K Parallel processor having central processor memory extension
IT1118570B (it) * 1979-04-19 1986-03-03 Cselt Centro Studi Lab Telecom Sistema per lo scambio di messaggi tra microilaboratori collegati da un mezzo trasmissivo sincrono
US4451882A (en) * 1981-11-20 1984-05-29 Dshkhunian Valery Data processing system
JPS58182758A (ja) * 1982-04-20 1983-10-25 Toshiba Corp 演算制御装置
US4703419A (en) * 1982-11-26 1987-10-27 Zenith Electronics Corporation Switchcover means and method for dual mode microprocessor system
US5003466A (en) * 1987-02-06 1991-03-26 At&T Bell Laboratories Multiprocessing method and arrangement
US4965720A (en) * 1988-07-18 1990-10-23 International Business Machines Corporation Directed address generation for virtual-address data processors
DE68913695T2 (de) * 1988-12-27 1994-10-20 Nec Corp Mikrorechner mit einem elektrisch löschbaren und programmierbaren nichtflüchtigen Speicher.
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5325517A (en) * 1989-05-17 1994-06-28 International Business Machines Corporation Fault tolerant data processing system
US5822570A (en) * 1996-10-30 1998-10-13 Microsoft Corporation System and method for parsing and executing a single instruction stream using a plurality of tightly coupled parsing and execution units
US7443196B2 (en) * 2005-07-15 2008-10-28 Tabula, Inc. Configuration network for a configurable IC
US7904759B2 (en) * 2006-01-11 2011-03-08 Amazon Technologies, Inc. System and method for service availability management
US9037698B1 (en) 2006-03-14 2015-05-19 Amazon Technologies, Inc. Method and system for collecting and analyzing time-series data
US7979439B1 (en) 2006-03-14 2011-07-12 Amazon Technologies, Inc. Method and system for collecting and analyzing time-series data
US8601112B1 (en) 2006-03-14 2013-12-03 Amazon Technologies, Inc. Method and system for collecting and analyzing time-series data

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3229260A (en) * 1962-03-02 1966-01-11 Ibm Multiprocessing computer system
US3444525A (en) * 1966-04-15 1969-05-13 Gen Electric Centrally controlled multicomputer system
US3566358A (en) * 1968-03-19 1971-02-23 Bevier Hasbrouck Integrated multi-computer system
US3668650A (en) * 1970-07-23 1972-06-06 Contrologic Inc Single package basic processor unit with synchronous and asynchronous timing control
US3766532A (en) * 1972-04-28 1973-10-16 Nanodata Corp Data processing system having two levels of program control
JPS5740531B2 (fr) * 1973-10-08 1982-08-28

Also Published As

Publication number Publication date
DE2755616C2 (de) 1985-11-07
FR2375662B1 (fr) 1980-12-19
US4077060A (en) 1978-02-28
DE2755616A1 (de) 1978-06-29
IT1126217B (it) 1986-05-14
JPS5382241A (en) 1978-07-20
GB1589179A (en) 1981-05-07
JPS5637579B2 (fr) 1981-09-01

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