FR2375655B1 - - Google Patents

Info

Publication number
FR2375655B1
FR2375655B1 FR7738258A FR7738258A FR2375655B1 FR 2375655 B1 FR2375655 B1 FR 2375655B1 FR 7738258 A FR7738258 A FR 7738258A FR 7738258 A FR7738258 A FR 7738258A FR 2375655 B1 FR2375655 B1 FR 2375655B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7738258A
Other versions
FR2375655A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Original Assignee
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova filed Critical Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Publication of FR2375655A1 publication Critical patent/FR2375655A1/fr
Application granted granted Critical
Publication of FR2375655B1 publication Critical patent/FR2375655B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Complex Calculations (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
FR7738258A 1976-12-22 1977-12-19 Additionneur de codes de fibonacci Granted FR2375655A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762432391A SU732864A1 (ru) 1976-12-22 1976-12-22 Сумматор кодов фибоначчи

Publications (2)

Publication Number Publication Date
FR2375655A1 FR2375655A1 (fr) 1978-07-21
FR2375655B1 true FR2375655B1 (fr) 1980-08-22

Family

ID=20687540

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7738258A Granted FR2375655A1 (fr) 1976-12-22 1977-12-19 Additionneur de codes de fibonacci

Country Status (9)

Country Link
US (1) US4159529A (fr)
JP (1) JPS53101242A (fr)
CA (1) CA1103807A (fr)
DD (1) DD136317A1 (fr)
DE (1) DE2756832A1 (fr)
FR (1) FR2375655A1 (fr)
GB (1) GB1565460A (fr)
PL (1) PL109971B1 (fr)
SU (1) SU732864A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU840891A1 (ru) * 1978-05-15 1981-06-23 Винницкийполитехнический Институт Параллельный сумматор кодов фибоначчи
ATE201943T1 (de) * 1995-02-03 2001-06-15 Koninkl Philips Electronics Nv Anordnung zum kodieren einer sequenz von (n-1)- bit informationswörtern in eine sequenz von n-bit kanalwörtern sowie dekodieranordnung zum dekodieren einer sequenz von n-bit kanalwörtern in eine sequenz von (n-1)-bit informationswörtern
US6934733B1 (en) * 2001-12-12 2005-08-23 Lsi Logic Corporation Optimization of adder based circuit architecture
CN112787658B (zh) * 2020-12-31 2022-12-13 卓尔智联(武汉)研究院有限公司 基于斐波那契进制的逻辑运算电路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1547633A (fr) * 1967-10-16 1968-11-29 Labo Cent Telecommunicat Circuit d'addition de nombres binaires provenant du codage non linéaire de signaux

Also Published As

Publication number Publication date
SU732864A1 (ru) 1980-05-05
PL109971B1 (en) 1980-06-30
DD136317A1 (de) 1979-06-27
FR2375655A1 (fr) 1978-07-21
US4159529A (en) 1979-06-26
CA1103807A (fr) 1981-06-23
GB1565460A (en) 1980-04-23
PL203158A1 (pl) 1978-12-18
JPS53101242A (en) 1978-09-04
DE2756832A1 (de) 1978-07-06
JPS573100B2 (fr) 1982-01-20

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Legal Events

Date Code Title Description
ST Notification of lapse