FR2374792B1 - - Google Patents

Info

Publication number
FR2374792B1
FR2374792B1 FR7733126A FR7733126A FR2374792B1 FR 2374792 B1 FR2374792 B1 FR 2374792B1 FR 7733126 A FR7733126 A FR 7733126A FR 7733126 A FR7733126 A FR 7733126A FR 2374792 B1 FR2374792 B1 FR 2374792B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7733126A
Other versions
FR2374792A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2374792A1 publication Critical patent/FR2374792A1/fr
Application granted granted Critical
Publication of FR2374792B1 publication Critical patent/FR2374792B1/fr
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04FTIME-INTERVAL MEASURING
    • G04F10/00Apparatus for measuring unknown time intervals by electric means
    • G04F10/04Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an AC
    • GPHYSICS
    • G04HOROLOGY
    • G04FTIME-INTERVAL MEASURING
    • G04F10/00Apparatus for measuring unknown time intervals by electric means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)
  • Measurement Of Predetermined Time Intervals (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Debugging And Monitoring (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
FR7733126A 1976-12-20 1977-10-27 Dispositif de synchronisation a intervalle indetermine utilisant un registre a decalage de longueur variable Granted FR2374792A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/752,335 US4077011A (en) 1976-12-20 1976-12-20 Uncertain interval timer using a variable length shift register

Publications (2)

Publication Number Publication Date
FR2374792A1 FR2374792A1 (fr) 1978-07-13
FR2374792B1 true FR2374792B1 (fr) 1980-08-08

Family

ID=25025870

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7733126A Granted FR2374792A1 (fr) 1976-12-20 1977-10-27 Dispositif de synchronisation a intervalle indetermine utilisant un registre a decalage de longueur variable

Country Status (6)

Country Link
US (1) US4077011A (fr)
JP (1) JPS5376718A (fr)
DE (1) DE2752882A1 (fr)
FR (1) FR2374792A1 (fr)
GB (1) GB1540200A (fr)
IT (1) IT1113682B (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4184402A (en) * 1976-12-27 1980-01-22 Kabushiki Kaisha Kawai Gakki Seisakusho Electronic musical instrument
JPS5440537A (en) * 1977-09-07 1979-03-30 Hitachi Ltd Pipeline control system
DE2923963C2 (de) * 1979-06-13 1986-03-27 Endress U. Hauser Gmbh U. Co, 7867 Maulburg Verfahren zur Impulsabstandsmessung und Anordnung zur Durchführung des Verfahrens
FR2518779B1 (fr) * 1981-12-23 1987-09-18 Europ Teletransmission Dispositif de gestion d'une memoire commune a plusieurs processeurs
JPS5941533U (ja) * 1982-09-10 1984-03-17 井上エムテ−ビ−株式会社 装飾積層材
US4646300A (en) * 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
US4851987A (en) * 1986-01-17 1989-07-25 International Business Machines Corporation System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur
US5377170A (en) * 1992-04-11 1994-12-27 Blaylock; Randy W. Uteral contraction timer
US7167924B1 (en) 1996-06-10 2007-01-23 Diebold, Incorporated Financial transaction processing system and method
US6039245A (en) 1996-06-10 2000-03-21 Diebold, Incorporated Financial transaction processing system and method
US20100235784A1 (en) 2009-03-16 2010-09-16 Bas Ording Methods and Graphical User Interfaces for Editing on a Multifunction Device with a Touch Screen Display
US9715875B2 (en) 2014-05-30 2017-07-25 Apple Inc. Reducing the need for manual start/end-pointing and trigger phrases
US9734193B2 (en) 2014-05-30 2017-08-15 Apple Inc. Determining domain salience ranking from ambiguous words in natural speech
US9721566B2 (en) 2015-03-08 2017-08-01 Apple Inc. Competing devices responding to voice triggers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3434115A (en) * 1966-07-15 1969-03-18 Ibm Timed operation sequence controller
GB1415169A (en) * 1971-11-29 1975-11-26 Philips Nv Timed programme switching arrangement
US3745475A (en) * 1971-12-07 1973-07-10 Nasa Measurement system
US3863224A (en) * 1973-01-30 1975-01-28 Gen Electric Selectively controllable shift register and counter divider network
US3851154A (en) * 1973-12-19 1974-11-26 Bell Telephone Labor Inc Output preview arrangement for shift registers

Also Published As

Publication number Publication date
IT1113682B (it) 1986-01-20
DE2752882A1 (de) 1978-06-22
JPS5376718A (en) 1978-07-07
US4077011A (en) 1978-02-28
FR2374792A1 (fr) 1978-07-13
JPS5741731B2 (fr) 1982-09-04
GB1540200A (en) 1979-02-07

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Legal Events

Date Code Title Description
ST Notification of lapse