FR2368549A1 - Procede de traitement d'une couche d'oxyde mince sur un substrat de silicium - Google Patents

Procede de traitement d'une couche d'oxyde mince sur un substrat de silicium

Info

Publication number
FR2368549A1
FR2368549A1 FR7730144A FR7730144A FR2368549A1 FR 2368549 A1 FR2368549 A1 FR 2368549A1 FR 7730144 A FR7730144 A FR 7730144A FR 7730144 A FR7730144 A FR 7730144A FR 2368549 A1 FR2368549 A1 FR 2368549A1
Authority
FR
France
Prior art keywords
treating
oxide layer
silicon substrate
thin oxide
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR7730144A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CBS Corp
Original Assignee
Westinghouse Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westinghouse Electric Corp filed Critical Westinghouse Electric Corp
Publication of FR2368549A1 publication Critical patent/FR2368549A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

a. Procédé de traitement d'une couche d'oxyde mince sur un substrat de silicium. b. Procédé caractérisé en ce qu'on chauffe le substrat tout en le balayant avec un gaz inerte essentiellement pur, on introduit de l'acide chlorhydrique anhydre HCL dans la veine de gaz inerte balayant le substrat, on arrête l'introduction d'acide chlorhydrique anhydre HCL et on laisse le substrat se refroidir.
FR7730144A 1976-10-19 1977-10-06 Procede de traitement d'une couche d'oxyde mince sur un substrat de silicium Pending FR2368549A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/733,746 US4098924A (en) 1976-10-19 1976-10-19 Gate fabrication method for mnos memory devices

Publications (1)

Publication Number Publication Date
FR2368549A1 true FR2368549A1 (fr) 1978-05-19

Family

ID=24948959

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7730144A Pending FR2368549A1 (fr) 1976-10-19 1977-10-06 Procede de traitement d'une couche d'oxyde mince sur un substrat de silicium

Country Status (4)

Country Link
US (1) US4098924A (fr)
JP (1) JPS5350979A (fr)
DE (1) DE2746941A1 (fr)
FR (1) FR2368549A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4223048A (en) * 1978-08-07 1980-09-16 Pacific Western Systems Plasma enhanced chemical vapor processing of semiconductive wafers
US4401691A (en) * 1978-12-18 1983-08-30 Burroughs Corporation Oxidation of silicon wafers to eliminate white ribbon
US4455742A (en) * 1982-06-07 1984-06-26 Westinghouse Electric Corp. Method of making self-aligned memory MNOS-transistor
US5930631A (en) * 1996-07-19 1999-07-27 Mosel Vitelic Inc. Method of making double-poly MONOS flash EEPROM cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3647535A (en) * 1969-10-27 1972-03-07 Ncr Co Method of controllably oxidizing a silicon wafer
US3692571A (en) * 1970-11-12 1972-09-19 Northern Electric Co Method of reducing the mobile ion contamination in thermally grown silicon dioxide
US3719866A (en) * 1970-12-03 1973-03-06 Ncr Semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/76 *

Also Published As

Publication number Publication date
US4098924A (en) 1978-07-04
DE2746941A1 (de) 1978-04-20
JPS5350979A (en) 1978-05-09

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