FR2365179B1 - - Google Patents
Info
- Publication number
- FR2365179B1 FR2365179B1 FR7727200A FR7727200A FR2365179B1 FR 2365179 B1 FR2365179 B1 FR 2365179B1 FR 7727200 A FR7727200 A FR 7727200A FR 7727200 A FR7727200 A FR 7727200A FR 2365179 B1 FR2365179 B1 FR 2365179B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2641524A DE2641524B1 (de) | 1976-09-15 | 1976-09-15 | Anordnung zur Adressierung eines MOS-Speichers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2365179A1 FR2365179A1 (fr) | 1978-04-14 |
| FR2365179B1 true FR2365179B1 (US06534493-20030318-C00166.png) | 1983-05-13 |
Family
ID=5987981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7727200A Granted FR2365179A1 (fr) | 1976-09-15 | 1977-09-08 | Dispositif pour realiser l'adressage d'une memoire mos |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS6032279B2 (US06534493-20030318-C00166.png) |
| DE (1) | DE2641524B1 (US06534493-20030318-C00166.png) |
| FR (1) | FR2365179A1 (US06534493-20030318-C00166.png) |
| GB (1) | GB1588183A (US06534493-20030318-C00166.png) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6413289A (en) * | 1988-05-06 | 1989-01-18 | Nec Corp | Decoder circuit |
| KR100206598B1 (ko) * | 1995-12-29 | 1999-07-01 | 김영환 | 워드라인 구동 장치 |
| KR101412460B1 (ko) * | 2012-05-21 | 2014-07-01 | 주식회사 뉴핫맥스 | 발열 코일의 처짐 방지 구조를 갖는 히터 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3902082A (en) * | 1974-02-11 | 1975-08-26 | Mostek Corp | Dynamic data input latch and decoder |
-
1976
- 1976-09-15 DE DE2641524A patent/DE2641524B1/de active Granted
-
1977
- 1977-09-08 FR FR7727200A patent/FR2365179A1/fr active Granted
- 1977-09-12 JP JP52109774A patent/JPS6032279B2/ja not_active Expired
- 1977-09-13 GB GB3806177A patent/GB1588183A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6032279B2 (ja) | 1985-07-26 |
| DE2641524B1 (de) | 1977-11-17 |
| DE2641524C2 (US06534493-20030318-C00166.png) | 1978-07-13 |
| JPS5336147A (en) | 1978-04-04 |
| FR2365179A1 (fr) | 1978-04-14 |
| GB1588183A (en) | 1981-04-15 |
