FR2363233A1 - Clock signal generator for signal processing circuit - has controlled signal phase lag, using two frequency divider counters - Google Patents

Clock signal generator for signal processing circuit - has controlled signal phase lag, using two frequency divider counters

Info

Publication number
FR2363233A1
FR2363233A1 FR7626124A FR7626124A FR2363233A1 FR 2363233 A1 FR2363233 A1 FR 2363233A1 FR 7626124 A FR7626124 A FR 7626124A FR 7626124 A FR7626124 A FR 7626124A FR 2363233 A1 FR2363233 A1 FR 2363233A1
Authority
FR
France
Prior art keywords
phase lag
clock
processing circuit
frequency divider
signal generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7626124A
Other languages
French (fr)
Other versions
FR2363233B1 (en
Inventor
Roger Sassoon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Priority to FR7626124A priority Critical patent/FR2363233A1/en
Publication of FR2363233A1 publication Critical patent/FR2363233A1/en
Application granted granted Critical
Publication of FR2363233B1 publication Critical patent/FR2363233B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15006—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two programmable outputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The clock signal generator supplies clock signals with a controlled phase lag, for use in a signal processing circuit, to compensate introduced phase errors. It employs two frequency divider counters, each supplied with the clock frequency signal and each supplying an output frequency which is a given fraction of the clock frequency. The second counter has secondary inputs for displaying a count value and a position control input for the count value displayed. A logic circuit coupled to the counters responds to the first counter exceeding a given count value, to control the position of the second conter to the value displayed, the latter controlling the phase lag between the two counter outputs, supplied to respective outputs of the clock signal generator.
FR7626124A 1976-08-30 1976-08-30 Clock signal generator for signal processing circuit - has controlled signal phase lag, using two frequency divider counters Granted FR2363233A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7626124A FR2363233A1 (en) 1976-08-30 1976-08-30 Clock signal generator for signal processing circuit - has controlled signal phase lag, using two frequency divider counters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7626124A FR2363233A1 (en) 1976-08-30 1976-08-30 Clock signal generator for signal processing circuit - has controlled signal phase lag, using two frequency divider counters

Publications (2)

Publication Number Publication Date
FR2363233A1 true FR2363233A1 (en) 1978-03-24
FR2363233B1 FR2363233B1 (en) 1979-03-02

Family

ID=9177223

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7626124A Granted FR2363233A1 (en) 1976-08-30 1976-08-30 Clock signal generator for signal processing circuit - has controlled signal phase lag, using two frequency divider counters

Country Status (1)

Country Link
FR (1) FR2363233A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2522903A1 (en) * 1982-03-05 1983-09-09 Ampex METHOD AND CIRCUIT FOR PRODUCING SYNCHRONOUS CLOCK SIGNALS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2522903A1 (en) * 1982-03-05 1983-09-09 Ampex METHOD AND CIRCUIT FOR PRODUCING SYNCHRONOUS CLOCK SIGNALS

Also Published As

Publication number Publication date
FR2363233B1 (en) 1979-03-02

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Legal Events

Date Code Title Description
TP Transmission of property
ST Notification of lapse