FR2345859B1 - - Google Patents
Info
- Publication number
- FR2345859B1 FR2345859B1 FR7703513A FR7703513A FR2345859B1 FR 2345859 B1 FR2345859 B1 FR 2345859B1 FR 7703513 A FR7703513 A FR 7703513A FR 7703513 A FR7703513 A FR 7703513A FR 2345859 B1 FR2345859 B1 FR 2345859B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19762612666 DE2612666C2 (de) | 1976-03-25 | 1976-03-25 | Integrierte, invertierende logische Schaltung |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2345859A1 FR2345859A1 (fr) | 1977-10-21 |
FR2345859B1 true FR2345859B1 (es) | 1980-02-08 |
Family
ID=5973395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7703513A Granted FR2345859A1 (fr) | 1976-03-25 | 1977-02-01 | Circuit logique d'inversion hautement integre |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS52117036A (es) |
DE (1) | DE2612666C2 (es) |
FR (1) | FR2345859A1 (es) |
GB (1) | GB1569800A (es) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2816949C3 (de) * | 1978-04-19 | 1981-07-16 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierte Halbleiteranordnung und deren Verwendung zum Aufbau einer Speicheranordnung |
US4221977A (en) * | 1978-12-11 | 1980-09-09 | Motorola, Inc. | Static I2 L ram |
DE2855866C3 (de) * | 1978-12-22 | 1981-10-29 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren und Schaltungsanordnung zum Betreiben eines integrierten Halbleiterspeichers |
DE2926514A1 (de) * | 1979-06-30 | 1981-01-15 | Ibm Deutschland | Elektrische speicheranordnung und verfahren zu ihrem betrieb |
DE3174546D1 (en) * | 1981-05-30 | 1986-06-12 | Ibm Deutschland | High-speed large-scale integrated memory with bipolar transistors |
DE3380678D1 (en) * | 1983-05-25 | 1989-11-09 | Ibm Deutschland | Semiconductor memory |
DE3483265D1 (de) * | 1984-06-25 | 1990-10-25 | Ibm | Mtl-speicherzelle mit inhaerenter mehrfachfaehigkeit. |
DE3572244D1 (en) * | 1985-03-29 | 1989-09-14 | Ibm Deutschland | Stability testing of semiconductor memories |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3815106A (en) * | 1972-05-11 | 1974-06-04 | S Wiedmann | Flip-flop memory cell arrangement |
DE2021824C3 (de) * | 1970-05-05 | 1980-08-14 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithische Halbleiterschaltung |
US3816758A (en) * | 1971-04-14 | 1974-06-11 | Ibm | Digital logic circuit |
DE2356301C3 (de) * | 1973-11-10 | 1982-03-11 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierte, logische Schaltung |
-
1976
- 1976-03-25 DE DE19762612666 patent/DE2612666C2/de not_active Expired
-
1977
- 1977-02-01 FR FR7703513A patent/FR2345859A1/fr active Granted
- 1977-02-03 JP JP1031977A patent/JPS52117036A/ja active Pending
- 1977-03-02 GB GB870077A patent/GB1569800A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2612666C2 (de) | 1982-11-18 |
GB1569800A (en) | 1980-06-18 |
FR2345859A1 (fr) | 1977-10-21 |
DE2612666A1 (de) | 1977-09-29 |
JPS52117036A (en) | 1977-10-01 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |