FR2344071A1 - Procede et dispositif pour executer selectivement une addition binaire ou une addition bcd - Google Patents

Procede et dispositif pour executer selectivement une addition binaire ou une addition bcd

Info

Publication number
FR2344071A1
FR2344071A1 FR7706720A FR7706720A FR2344071A1 FR 2344071 A1 FR2344071 A1 FR 2344071A1 FR 7706720 A FR7706720 A FR 7706720A FR 7706720 A FR7706720 A FR 7706720A FR 2344071 A1 FR2344071 A1 FR 2344071A1
Authority
FR
France
Prior art keywords
addition
bcd
selectively executing
binary
binary addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7706720A
Other languages
English (en)
French (fr)
Other versions
FR2344071B1 (cs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2344071A1 publication Critical patent/FR2344071A1/fr
Application granted granted Critical
Publication of FR2344071B1 publication Critical patent/FR2344071B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
FR7706720A 1976-03-08 1977-03-08 Procede et dispositif pour executer selectivement une addition binaire ou une addition bcd Granted FR2344071A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66446076A 1976-03-08 1976-03-08

Publications (2)

Publication Number Publication Date
FR2344071A1 true FR2344071A1 (fr) 1977-10-07
FR2344071B1 FR2344071B1 (cs) 1981-10-02

Family

ID=24666056

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7706720A Granted FR2344071A1 (fr) 1976-03-08 1977-03-08 Procede et dispositif pour executer selectivement une addition binaire ou une addition bcd

Country Status (4)

Country Link
JP (1) JPS52108745A (cs)
DE (1) DE2708637C3 (cs)
FR (1) FR2344071A1 (cs)
GB (1) GB1525893A (cs)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2745648A1 (fr) * 1996-02-27 1997-09-05 Denso Corp Additionneur a lecture anticipee de report et son circuit d'operations logiques

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3112396A (en) * 1957-05-03 1963-11-26 Ibm Arithmetic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2745648A1 (fr) * 1996-02-27 1997-09-05 Denso Corp Additionneur a lecture anticipee de report et son circuit d'operations logiques

Also Published As

Publication number Publication date
JPS52108745A (en) 1977-09-12
GB1525893A (en) 1978-09-20
FR2344071B1 (cs) 1981-10-02
DE2708637B2 (de) 1980-06-19
DE2708637C3 (de) 1985-07-18
JPS5534454B2 (cs) 1980-09-06
DE2708637A1 (de) 1977-09-15

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