FR2335102A1 - Dispositif de decodage d'un message en code biphase differentiel - Google Patents

Dispositif de decodage d'un message en code biphase differentiel

Info

Publication number
FR2335102A1
FR2335102A1 FR7531694A FR7531694A FR2335102A1 FR 2335102 A1 FR2335102 A1 FR 2335102A1 FR 7531694 A FR7531694 A FR 7531694A FR 7531694 A FR7531694 A FR 7531694A FR 2335102 A1 FR2335102 A1 FR 2335102A1
Authority
FR
France
Prior art keywords
message
pulse
local clock
decoding
phase differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7531694A
Other languages
English (en)
French (fr)
Other versions
FR2335102B1 (enExample
Inventor
Jean-Pierre Houdard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Inc
Original Assignee
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Inc filed Critical Nokia Inc
Priority to FR7531694A priority Critical patent/FR2335102A1/fr
Publication of FR2335102A1 publication Critical patent/FR2335102A1/fr
Application granted granted Critical
Publication of FR2335102B1 publication Critical patent/FR2335102B1/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
FR7531694A 1975-10-16 1975-10-16 Dispositif de decodage d'un message en code biphase differentiel Granted FR2335102A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7531694A FR2335102A1 (fr) 1975-10-16 1975-10-16 Dispositif de decodage d'un message en code biphase differentiel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7531694A FR2335102A1 (fr) 1975-10-16 1975-10-16 Dispositif de decodage d'un message en code biphase differentiel

Publications (2)

Publication Number Publication Date
FR2335102A1 true FR2335102A1 (fr) 1977-07-08
FR2335102B1 FR2335102B1 (enExample) 1978-05-12

Family

ID=9161272

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7531694A Granted FR2335102A1 (fr) 1975-10-16 1975-10-16 Dispositif de decodage d'un message en code biphase differentiel

Country Status (1)

Country Link
FR (1) FR2335102A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2542535A1 (fr) * 1983-03-11 1984-09-14 Cit Alcatel Procede de transmission synchrone de donnees et systeme pour sa mise en oeuvre
FR2542532A1 (fr) * 1983-03-11 1984-09-14 Cit Alcatel Circuit de recuperation du rythme d'une transmission synchrone de donnees utilisant une combinaison des codes biphase l et biphase modifie
EP0121750A1 (fr) * 1983-03-11 1984-10-17 Alcatel Circuit de récupération du rythme d'une transmission synchrone de données utilisant une combinaison des codes biphase L et biphase modifié

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN" VOLUME 17, NO.7, DECEMBRE 1974. ARTICLE DE DWIRE: "FIXED TIME BASE F2F DATA CLOCK SEPARATOR CIRCUIT" PAGES 2109-2110.) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2542535A1 (fr) * 1983-03-11 1984-09-14 Cit Alcatel Procede de transmission synchrone de donnees et systeme pour sa mise en oeuvre
FR2542532A1 (fr) * 1983-03-11 1984-09-14 Cit Alcatel Circuit de recuperation du rythme d'une transmission synchrone de donnees utilisant une combinaison des codes biphase l et biphase modifie
EP0121750A1 (fr) * 1983-03-11 1984-10-17 Alcatel Circuit de récupération du rythme d'une transmission synchrone de données utilisant une combinaison des codes biphase L et biphase modifié

Also Published As

Publication number Publication date
FR2335102B1 (enExample) 1978-05-12

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Legal Events

Date Code Title Description
ST Notification of lapse