FR2326807A1 - Circuit de traitement de signaux asynchrones - Google Patents

Circuit de traitement de signaux asynchrones

Info

Publication number
FR2326807A1
FR2326807A1 FR7629640A FR7629640A FR2326807A1 FR 2326807 A1 FR2326807 A1 FR 2326807A1 FR 7629640 A FR7629640 A FR 7629640A FR 7629640 A FR7629640 A FR 7629640A FR 2326807 A1 FR2326807 A1 FR 2326807A1
Authority
FR
France
Prior art keywords
signal processing
processing circuit
asynchronous signal
asynchronous
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7629640A
Other languages
English (en)
Other versions
FR2326807B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11929175A external-priority patent/JPS5243346A/ja
Priority claimed from JP4522176A external-priority patent/JPS52128045A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2326807A1 publication Critical patent/FR2326807A1/fr
Application granted granted Critical
Publication of FR2326807B1 publication Critical patent/FR2326807B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
FR7629640A 1975-10-01 1976-10-01 Circuit de traitement de signaux asynchrones Granted FR2326807A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11929175A JPS5243346A (en) 1975-10-01 1975-10-01 Symbol convertible circuit
JP4522176A JPS52128045A (en) 1976-04-20 1976-04-20 Synchronous system signal processing circuit

Publications (2)

Publication Number Publication Date
FR2326807A1 true FR2326807A1 (fr) 1977-04-29
FR2326807B1 FR2326807B1 (fr) 1982-08-13

Family

ID=26385195

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7629640A Granted FR2326807A1 (fr) 1975-10-01 1976-10-01 Circuit de traitement de signaux asynchrones

Country Status (3)

Country Link
DE (1) DE2644181C2 (fr)
FR (1) FR2326807A1 (fr)
GB (1) GB1553091A (fr)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2950348A (en) * 1954-08-03 1960-08-23 Philco Corp Combined encoder and decoder system

Also Published As

Publication number Publication date
DE2644181C2 (de) 1982-05-13
DE2644181A1 (de) 1977-04-07
GB1553091A (en) 1979-09-19
FR2326807B1 (fr) 1982-08-13

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Legal Events

Date Code Title Description
ST Notification of lapse