FR2324360A1 - Procede de formation de couches minces de silicium monocristallin de haute qualite sur des substrats isolants - Google Patents

Procede de formation de couches minces de silicium monocristallin de haute qualite sur des substrats isolants

Info

Publication number
FR2324360A1
FR2324360A1 FR7401045A FR7401045A FR2324360A1 FR 2324360 A1 FR2324360 A1 FR 2324360A1 FR 7401045 A FR7401045 A FR 7401045A FR 7401045 A FR7401045 A FR 7401045A FR 2324360 A1 FR2324360 A1 FR 2324360A1
Authority
FR
France
Prior art keywords
high quality
thin layers
insulating substrates
forming thin
monocristalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7401045A
Other languages
English (en)
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2324360A1 publication Critical patent/FR2324360A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
FR7401045A 1973-01-12 1974-01-11 Procede de formation de couches minces de silicium monocristallin de haute qualite sur des substrats isolants Withdrawn FR2324360A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US323011A US3929528A (en) 1973-01-12 1973-01-12 Fabrication of monocriptalline silicon on insulating substrates utilizing selective etching and deposition techniques

Publications (1)

Publication Number Publication Date
FR2324360A1 true FR2324360A1 (fr) 1977-04-15

Family

ID=23257410

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7401045A Withdrawn FR2324360A1 (fr) 1973-01-12 1974-01-11 Procede de formation de couches minces de silicium monocristallin de haute qualite sur des substrats isolants

Country Status (4)

Country Link
US (1) US3929528A (online.php)
JP (1) JPS49110284A (online.php)
DE (1) DE2401380A1 (online.php)
FR (1) FR2324360A1 (online.php)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329551B2 (online.php) * 1974-08-19 1978-08-22
US4092209A (en) * 1976-12-30 1978-05-30 Rca Corp. Silicon implanted and bombarded with phosphorus ions
US4234361A (en) * 1979-07-05 1980-11-18 Wisconsin Alumni Research Foundation Process for producing an electrostatically deformable thin silicon membranes utilizing a two-stage diffusion step to form an etchant resistant layer
US4372803A (en) * 1980-09-26 1983-02-08 The United States Of America As Represented By The Secretary Of The Navy Method for etch thinning silicon devices
JPS60182149A (ja) * 1984-02-28 1985-09-17 Matsushita Electronics Corp 半導体集積回路の製造方法
US4662956A (en) * 1985-04-01 1987-05-05 Motorola, Inc. Method for prevention of autodoping of epitaxial layers
US5001075A (en) * 1989-04-03 1991-03-19 Motorola Fabrication of dielectrically isolated semiconductor device
US5145795A (en) * 1990-06-25 1992-09-08 Motorola, Inc. Semiconductor device and method therefore
US5264070A (en) * 1990-10-09 1993-11-23 Motorola, Inc. Method of growth-orientation of a crystal on a device using an oriented seed layer
EP0483487B1 (en) * 1990-10-31 1995-03-01 International Business Machines Corporation Self-aligned epitaxial base transistor and method for fabricating same
US5234846A (en) * 1992-04-30 1993-08-10 International Business Machines Corporation Method of making bipolar transistor with reduced topography
US5334281A (en) * 1992-04-30 1994-08-02 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5444014A (en) * 1994-12-16 1995-08-22 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
US6159285A (en) * 1998-05-07 2000-12-12 Virginia Semiconductor, Inc. Converting <100> and <111> ingots to <110> ingots
US8809202B2 (en) * 2012-02-14 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices including use of a protective material

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3429756A (en) * 1965-02-05 1969-02-25 Monsanto Co Method for the preparation of inorganic single crystal and polycrystalline electronic materials
US3587166A (en) * 1965-02-26 1971-06-28 Texas Instruments Inc Insulated isolation techniques in integrated circuits
US3721588A (en) * 1971-08-13 1973-03-20 Motorola Inc Thin single crystal silicon on an insulating substrate and improved dielectric isolation processing method

Also Published As

Publication number Publication date
US3929528A (en) 1975-12-30
DE2401380A1 (de) 1974-07-25
JPS49110284A (online.php) 1974-10-21

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Legal Events

Date Code Title Description
ST Notification of lapse