FR2301870A1 - Circuit multiplicateur a fort debit numerique notamment pour filtre numerique - Google Patents

Circuit multiplicateur a fort debit numerique notamment pour filtre numerique

Info

Publication number
FR2301870A1
FR2301870A1 FR7505161A FR7505161A FR2301870A1 FR 2301870 A1 FR2301870 A1 FR 2301870A1 FR 7505161 A FR7505161 A FR 7505161A FR 7505161 A FR7505161 A FR 7505161A FR 2301870 A1 FR2301870 A1 FR 2301870A1
Authority
FR
France
Prior art keywords
digital
multiplier circuit
flow multiplier
digital filter
filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7505161A
Other languages
English (en)
Other versions
FR2301870B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR7505161A priority Critical patent/FR2301870A1/fr
Priority to DE19762605495 priority patent/DE2605495B2/de
Priority to GB6060/76A priority patent/GB1541697A/en
Priority to US05/659,038 priority patent/US4027147A/en
Publication of FR2301870A1 publication Critical patent/FR2301870A1/fr
Application granted granted Critical
Publication of FR2301870B1 publication Critical patent/FR2301870B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
FR7505161A 1975-02-19 1975-02-19 Circuit multiplicateur a fort debit numerique notamment pour filtre numerique Granted FR2301870A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR7505161A FR2301870A1 (fr) 1975-02-19 1975-02-19 Circuit multiplicateur a fort debit numerique notamment pour filtre numerique
DE19762605495 DE2605495B2 (de) 1975-02-19 1976-02-12 Multiplikationsschaltung, insbesondere zum filtern von zeitmultiplexinformationen
GB6060/76A GB1541697A (en) 1975-02-19 1976-02-17 High rate binary multiplication unit
US05/659,038 US4027147A (en) 1975-02-19 1976-02-18 Binary multiplication unit with partial product and sum calculation time higher than multiplicand bit interval

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7505161A FR2301870A1 (fr) 1975-02-19 1975-02-19 Circuit multiplicateur a fort debit numerique notamment pour filtre numerique

Publications (2)

Publication Number Publication Date
FR2301870A1 true FR2301870A1 (fr) 1976-09-17
FR2301870B1 FR2301870B1 (fr) 1977-11-10

Family

ID=9151430

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7505161A Granted FR2301870A1 (fr) 1975-02-19 1975-02-19 Circuit multiplicateur a fort debit numerique notamment pour filtre numerique

Country Status (4)

Country Link
US (1) US4027147A (fr)
DE (1) DE2605495B2 (fr)
FR (1) FR2301870A1 (fr)
GB (1) GB1541697A (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163287A (en) * 1978-04-20 1979-07-31 Northern Telecom Limited Binary multiplier circuit including coding circuit
US4484300A (en) * 1980-12-24 1984-11-20 Honeywell Information Systems Inc. Data processor having units carry and tens carry apparatus supporting a decimal multiply operation
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit
US4947364A (en) * 1985-10-23 1990-08-07 Hewlett-Packard Company Method in a computing system for performing a multiplication
JPS6461121A (en) * 1987-08-31 1989-03-08 Mitsubishi Electric Corp Semiconductor integrated circuit
US5274707A (en) * 1991-12-06 1993-12-28 Roger Schlafly Modular exponentiation and reduction device and method
FI97002C (fi) * 1993-12-17 1996-09-25 Eero Juhani Pajarre Suora FIR-suodatin, menetelmä pistetulon laskemiseksi FIR-suodattimessa ja menetelmä suoran FIR-suodattimen suunnittelemiseksi

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691359A (en) * 1970-07-28 1972-09-12 Singer General Precision Asynchronous binary multiplier employing carry-save addition

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3795880A (en) 1972-06-19 1974-03-05 Ibm Partial product array multiplier
US3805043A (en) * 1972-10-11 1974-04-16 Bell Telephone Labor Inc Serial-parallel binary multiplication using pairwise addition
US3794820A (en) * 1972-10-16 1974-02-26 Philco Ford Corp Binary multiplier circuit
US3816732A (en) * 1973-03-29 1974-06-11 Rockland Systems Corp Apparatus and method for serial-parallel binary multiplication
US3947670A (en) * 1974-11-22 1976-03-30 General Electric Company Signed multiplication logic
US3956622A (en) * 1974-12-20 1976-05-11 Bell Telephone Laboratories, Incorporated Two's complement pipeline multiplier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691359A (en) * 1970-07-28 1972-09-12 Singer General Precision Asynchronous binary multiplier employing carry-save addition

Also Published As

Publication number Publication date
DE2605495B2 (de) 1977-11-24
DE2605495A1 (de) 1976-09-02
FR2301870B1 (fr) 1977-11-10
DE2605495C3 (fr) 1978-07-20
GB1541697A (en) 1979-03-07
US4027147A (en) 1977-05-31

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Legal Events

Date Code Title Description
ST Notification of lapse