FR2300397A1 - Switching circuit for programming facility for ECL ROM - has line selection circuits which allow setting voltage level to be applied for programming memory cells - Google Patents

Switching circuit for programming facility for ECL ROM - has line selection circuits which allow setting voltage level to be applied for programming memory cells

Info

Publication number
FR2300397A1
FR2300397A1 FR7603091A FR7603091A FR2300397A1 FR 2300397 A1 FR2300397 A1 FR 2300397A1 FR 7603091 A FR7603091 A FR 7603091A FR 7603091 A FR7603091 A FR 7603091A FR 2300397 A1 FR2300397 A1 FR 2300397A1
Authority
FR
France
Prior art keywords
programming
ecl
rom
memory cells
voltage level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7603091A
Other languages
French (fr)
Other versions
FR2300397B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2300397A1 publication Critical patent/FR2300397A1/en
Application granted granted Critical
Publication of FR2300397B1 publication Critical patent/FR2300397B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

A switching circuit provides a means of programming an ECL ROM. Each memory cell (SMA) in the matrix consists of a transistor (ST) and a fused resistance (RS). The memory cells are coupled to input lines (ZL) and output columns (SL). Address signals (Ao-A7) select the required lines and columns over address amplifiers (ADV1, ADV2). For the columns the amplifiers are coupled to a decoding circuit (DS) operating into four groups of switching stages (S5) and generating outputs to amplifiers (LV) during the read cycle. The line selection circuits (ZS) combine the dual function of selection and programming. For normal selection one voltage level is applied to one line and for programming a voltage sufficiency high for the resistance is applied.
FR7603091A 1975-02-07 1976-02-04 Switching circuit for programming facility for ECL ROM - has line selection circuits which allow setting voltage level to be applied for programming memory cells Granted FR2300397A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752505285 DE2505285C3 (en) 1975-02-07 1975-02-07 Circuit arrangement for setting the information in a programmable ECL read-only memory

Publications (2)

Publication Number Publication Date
FR2300397A1 true FR2300397A1 (en) 1976-09-03
FR2300397B1 FR2300397B1 (en) 1979-08-24

Family

ID=5938396

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7603091A Granted FR2300397A1 (en) 1975-02-07 1976-02-04 Switching circuit for programming facility for ECL ROM - has line selection circuits which allow setting voltage level to be applied for programming memory cells

Country Status (2)

Country Link
DE (1) DE2505285C3 (en)
FR (1) FR2300397A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0159928A2 (en) * 1984-03-23 1985-10-30 Fujitsu Limited Semiconductor integrated circuit device having fuse-type information storing circuit
EP0068058B1 (en) * 1981-06-25 1986-09-03 International Business Machines Corporation Electrically programmable read-only memory

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4276617A (en) * 1979-06-28 1981-06-30 Raytheon Company Transistor switching circuitry
US4639661A (en) * 1985-09-03 1987-01-27 Advanced Micro Devices, Inc. Power-down arrangement for an ECL circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1206159A (en) * 1966-12-30 1970-09-23 Texas Instruments Inc Integrated circuit components in insulated islands of integrated semiconductor materials in a single substrate
GB1262865A (en) * 1968-05-27 1972-02-09 Plessey Co Ltd Improvements in or relating to storage arrangements

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1206159A (en) * 1966-12-30 1970-09-23 Texas Instruments Inc Integrated circuit components in insulated islands of integrated semiconductor materials in a single substrate
GB1262865A (en) * 1968-05-27 1972-02-09 Plessey Co Ltd Improvements in or relating to storage arrangements

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0068058B1 (en) * 1981-06-25 1986-09-03 International Business Machines Corporation Electrically programmable read-only memory
EP0159928A2 (en) * 1984-03-23 1985-10-30 Fujitsu Limited Semiconductor integrated circuit device having fuse-type information storing circuit
EP0159928A3 (en) * 1984-03-23 1987-10-07 Fujitsu Limited Semiconductor integrated circuit device having fuse-type information storing circuit

Also Published As

Publication number Publication date
DE2505285A1 (en) 1976-08-19
DE2505285C3 (en) 1978-07-20
FR2300397B1 (en) 1979-08-24
DE2505285B2 (en) 1977-12-01

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Legal Events

Date Code Title Description
ST Notification of lapse