FR2298138A1 - Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status - Google Patents

Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status

Info

Publication number
FR2298138A1
FR2298138A1 FR7501326A FR7501326A FR2298138A1 FR 2298138 A1 FR2298138 A1 FR 2298138A1 FR 7501326 A FR7501326 A FR 7501326A FR 7501326 A FR7501326 A FR 7501326A FR 2298138 A1 FR2298138 A1 FR 2298138A1
Authority
FR
France
Prior art keywords
data processing
access
stages
operated
sequential phases
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7501326A
Other languages
French (fr)
Other versions
FR2298138B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to FR7501326A priority Critical patent/FR2298138A1/en
Publication of FR2298138A1 publication Critical patent/FR2298138A1/en
Application granted granted Critical
Publication of FR2298138B1 publication Critical patent/FR2298138B1/fr
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

A data processing system consists of a number of different processing stages that may be operated in a number of different sequential phases. Within each phase various stages of the system may be operated with different instruction sets. The system is analogous to an oil-pipeline with various control stages along its length. A main memory provides both programme instructions and operands. A section of the store is assigned as a stack memory. The first stage of the processing unit is a programme counter coupled to an instruction unit. The main memory is coupled to a fast access auxiliary store operating into the instruction register. A stack access unit operates in conjunction with a second auxiliary memory.
FR7501326A 1975-01-16 1975-01-16 Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status Granted FR2298138A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7501326A FR2298138A1 (en) 1975-01-16 1975-01-16 Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7501326A FR2298138A1 (en) 1975-01-16 1975-01-16 Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status

Publications (2)

Publication Number Publication Date
FR2298138A1 true FR2298138A1 (en) 1976-08-13
FR2298138B1 FR2298138B1 (en) 1982-03-19

Family

ID=9149905

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7501326A Granted FR2298138A1 (en) 1975-01-16 1975-01-16 Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status

Country Status (1)

Country Link
FR (1) FR2298138A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2455316A1 (en) * 1979-04-24 1980-11-21 Tektronix Inc ASSEMBLY AND METHOD INCLUDED IN A DIGITAL PROCESSING SYSTEM FOR PRE-READING OF CODES AND OPERATIONAL QUANTITIES

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2455316A1 (en) * 1979-04-24 1980-11-21 Tektronix Inc ASSEMBLY AND METHOD INCLUDED IN A DIGITAL PROCESSING SYSTEM FOR PRE-READING OF CODES AND OPERATIONAL QUANTITIES

Also Published As

Publication number Publication date
FR2298138B1 (en) 1982-03-19

Similar Documents

Publication Publication Date Title
JPS56149646A (en) Operation controller
EP0263447A3 (en) A method and apparatus for implementing a branch and return on address instruction in a digital data processing system
KR920001319A (en) Processor and treatment method
ES486103A1 (en) Data processing system having an integrated stack and register machine architecture.
JPS5672742A (en) Data processor
CA1018663A (en) Data processing system having an improved overlap instruction fetch and instruction execution feature
JPS5779557A (en) Data processor
FR2298138A1 (en) Data processing with stages operated to different sequential phases - using programmed memory with access to provide operating status
JPS57109084A (en) Schedule system for instruction in parallel computer having plural operating devices
Kilburn et al. The Manchester University Mark II digital-computing machine
JPS578851A (en) Parallel processing system
FR2378313A1 (en) Microprocessor memory access control system - uses exterior programme counter to process different lengths of instructions
JPS5657159A (en) Voice desk calculator
JPS5582357A (en) Information processing unit
JPS5674706A (en) Sequence control system
JPS5491151A (en) Internal memory control system on array processor
JPS5381019A (en) Control system for variable length data access
JPS5393743A (en) Collective arithmetic unit
JPS5671105A (en) Shift register type programmable controller with memory
FR2298139A1 (en) Data processing system with fast access auxiliary programme store - has programme store coupled to large capacity buffer controlled in groups over gating circuit
JPS6459537A (en) System for controlling cache memory of data processor
JPS5339032A (en) Branch control system
FR2286439A1 (en) Single memory unit access system for multiple central processors - has multiprocessor control for time shared address and data transfers
JPS57168345A (en) Data processing device
JPS5599652A (en) Microprogram control unit

Legal Events

Date Code Title Description
ST Notification of lapse