FR2286504B1 - - Google Patents
Info
- Publication number
- FR2286504B1 FR2286504B1 FR7528930A FR7528930A FR2286504B1 FR 2286504 B1 FR2286504 B1 FR 2286504B1 FR 7528930 A FR7528930 A FR 7528930A FR 7528930 A FR7528930 A FR 7528930A FR 2286504 B1 FR2286504 B1 FR 2286504B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742445594 DE2445594A1 (de) | 1974-09-24 | 1974-09-24 | Verfahren zur herstellung integrierter schaltungen |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2286504A1 FR2286504A1 (fr) | 1976-04-23 |
| FR2286504B1 true FR2286504B1 (no) | 1978-04-07 |
Family
ID=5926596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7528930A Granted FR2286504A1 (fr) | 1974-09-24 | 1975-09-22 | Procede pour la fabrication de circuits integres |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5160175A (no) |
| DE (1) | DE2445594A1 (no) |
| FR (1) | FR2286504A1 (no) |
| GB (1) | GB1514288A (no) |
| IT (1) | IT1042658B (no) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3218309A1 (de) * | 1982-05-14 | 1983-11-17 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von integrierten mos-feldeffekttransistoren mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2040180B2 (de) * | 1970-01-22 | 1977-08-25 | Intel Corp, Mountain View, Calif. (V.St.A.) | Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht |
| US3833919A (en) * | 1972-10-12 | 1974-09-03 | Ncr | Multilevel conductor structure and method |
-
1974
- 1974-09-24 DE DE19742445594 patent/DE2445594A1/de active Pending
-
1975
- 1975-08-28 GB GB3546475A patent/GB1514288A/en not_active Expired
- 1975-09-18 IT IT2737375A patent/IT1042658B/it active
- 1975-09-22 FR FR7528930A patent/FR2286504A1/fr active Granted
- 1975-09-25 JP JP11592675A patent/JPS5160175A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| IT1042658B (it) | 1980-01-30 |
| DE2445594A1 (de) | 1976-04-08 |
| GB1514288A (en) | 1978-06-14 |
| JPS5160175A (ja) | 1976-05-25 |
| FR2286504A1 (fr) | 1976-04-23 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |