FR2237549A5 - - Google Patents

Info

Publication number
FR2237549A5
FR2237549A5 FR7324282*A FR7324282A FR2237549A5 FR 2237549 A5 FR2237549 A5 FR 2237549A5 FR 7324282 A FR7324282 A FR 7324282A FR 2237549 A5 FR2237549 A5 FR 2237549A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7324282*A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR2237549A5 publication Critical patent/FR2237549A5/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR7324282*A 1972-07-24 1973-06-26 Expired FR2237549A5 (OSRAM)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00274771A US3829840A (en) 1972-07-24 1972-07-24 Virtual memory system

Publications (1)

Publication Number Publication Date
FR2237549A5 true FR2237549A5 (OSRAM) 1975-02-07

Family

ID=23049553

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7324282*A Expired FR2237549A5 (OSRAM) 1972-07-24 1973-06-26

Country Status (5)

Country Link
US (1) US3829840A (OSRAM)
JP (1) JPS4953339A (OSRAM)
CA (1) CA989521A (OSRAM)
FR (1) FR2237549A5 (OSRAM)
IT (1) IT988998B (OSRAM)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5615066B2 (OSRAM) * 1974-06-13 1981-04-08
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
DE2605617A1 (de) * 1976-02-12 1977-08-18 Siemens Ag Schaltungsanordnung zum adressieren von daten
US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4128875A (en) * 1976-12-16 1978-12-05 Sperry Rand Corporation Optional virtual memory system
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
US4357656A (en) * 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
US4241401A (en) * 1977-12-19 1980-12-23 Sperry Corporation Virtual address translator utilizing interrupt level code
US4376297A (en) * 1978-04-10 1983-03-08 Signetics Corporation Virtual memory addressing device
JPS5943786B2 (ja) * 1979-03-30 1984-10-24 パナフアコム株式会社 記憶装置のアクセス方式
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4410941A (en) * 1980-12-29 1983-10-18 Wang Laboratories, Inc. Computer having an indexed local ram to store previously translated virtual addresses
JPS5898893A (ja) * 1981-12-09 1983-06-11 Toshiba Corp 情報処理装置
JPS5948879A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 記憶制御方式
US4631660A (en) * 1983-08-30 1986-12-23 Amdahl Corporation Addressing system for an associative cache memory
JPH0616272B2 (ja) * 1984-06-27 1994-03-02 株式会社日立製作所 メモリアクセス制御方式
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
US4821171A (en) * 1985-05-07 1989-04-11 Prime Computer, Inc. System of selective purging of address translation in computer memories
US4774653A (en) * 1985-08-07 1988-09-27 Hewlett-Packard Company Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
US5347636A (en) * 1985-11-08 1994-09-13 Nec Corporation Data processor which efficiently accesses main memory and input/output devices
US5123101A (en) * 1986-11-12 1992-06-16 Xerox Corporation Multiple address space mapping technique for shared memory wherein a processor operates a fault handling routine upon a translator miss
JPH07120312B2 (ja) * 1987-10-07 1995-12-20 株式会社日立製作所 バッファメモリ制御装置
US5239635A (en) * 1988-06-06 1993-08-24 Digital Equipment Corporation Virtual address to physical address translation using page tables in virtual memory
FR2645987B1 (fr) * 1989-04-13 1991-06-07 Bull Sa Dispositif d'acceleration des acces memoire dans un systeme informatique
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
US5724551A (en) * 1996-05-23 1998-03-03 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage keys for controlling accesses to the buffers
US7356668B2 (en) * 2004-08-27 2008-04-08 Microsoft Corporation System and method for using address bits to form an index into secure memory
US7734926B2 (en) * 2004-08-27 2010-06-08 Microsoft Corporation System and method for applying security to memory reads and writes
US7653802B2 (en) * 2004-08-27 2010-01-26 Microsoft Corporation System and method for using address lines to control memory usage
US7822993B2 (en) * 2004-08-27 2010-10-26 Microsoft Corporation System and method for using address bits to affect encryption
US7444523B2 (en) * 2004-08-27 2008-10-28 Microsoft Corporation System and method for using address bits to signal security attributes of data in the address space
US9152570B2 (en) * 2012-02-27 2015-10-06 Vmware, Inc. System and method for supporting finer-grained copy-on-write page sizes

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
NL6815506A (OSRAM) * 1968-10-31 1970-05-04
FR10582E (fr) * 1970-06-29 1909-07-30 Paul Alexis Victor Lerolle Jeu de serrures avec passe-partout
US3701107A (en) * 1970-10-01 1972-10-24 Rca Corp Computer with probability means to transfer pages from large memory to fast memory
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing

Also Published As

Publication number Publication date
IT988998B (it) 1975-04-30
DE2332603B2 (de) 1974-11-21
JPS4953339A (OSRAM) 1974-05-23
US3829840A (en) 1974-08-13
CA989521A (en) 1976-05-18
DE2332603A1 (de) 1974-02-21

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Legal Events

Date Code Title Description
ST Notification of lapse