FR2202368A1 - - Google Patents

Info

Publication number
FR2202368A1
FR2202368A1 FR7335130A FR7335130A FR2202368A1 FR 2202368 A1 FR2202368 A1 FR 2202368A1 FR 7335130 A FR7335130 A FR 7335130A FR 7335130 A FR7335130 A FR 7335130A FR 2202368 A1 FR2202368 A1 FR 2202368A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7335130A
Other languages
French (fr)
Other versions
FR2202368B1 (enExample
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of FR2202368A1 publication Critical patent/FR2202368A1/fr
Application granted granted Critical
Publication of FR2202368B1 publication Critical patent/FR2202368B1/fr
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H10P14/61
    • H10P95/00
    • H10W10/0124
    • H10W10/0126
    • H10W10/0127
    • H10W10/13
    • H10W15/00
    • H10W15/01
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/018Compensation doping
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/117Oxidation, selective
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/145Shaped junctions
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/944Shadow
FR7335130A 1972-10-04 1973-10-02 Expired FR2202368B1 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47099008A JPS5228550B2 (enExample) 1972-10-04 1972-10-04

Publications (2)

Publication Number Publication Date
FR2202368A1 true FR2202368A1 (enExample) 1974-05-03
FR2202368B1 FR2202368B1 (enExample) 1977-09-16

Family

ID=14235013

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7335130A Expired FR2202368B1 (enExample) 1972-10-04 1973-10-02

Country Status (6)

Country Link
US (1) US3891469A (enExample)
JP (1) JPS5228550B2 (enExample)
DE (1) DE2349951A1 (enExample)
FR (1) FR2202368B1 (enExample)
GB (1) GB1436784A (enExample)
NL (1) NL7313681A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0236632A3 (en) * 1986-03-03 1988-10-05 Trw Inc. Formation of diffused buried layers

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5138983A (enExample) * 1974-09-30 1976-03-31 Hitachi Ltd
FR2341201A1 (fr) * 1976-02-16 1977-09-09 Radiotechnique Compelec Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu
US4137109A (en) * 1976-04-12 1979-01-30 Texas Instruments Incorporated Selective diffusion and etching method for isolation of integrated logic circuit
US4197143A (en) * 1976-09-03 1980-04-08 Fairchild Camera & Instrument Corporation Method of making a junction field-effect transistor utilizing a conductive buried region
US4064527A (en) * 1976-09-20 1977-12-20 Intersil, Inc. Integrated circuit having a buried load device
JPS5370687A (en) * 1976-12-07 1978-06-23 Toshiba Corp Production of semiconductor device
JPS55153344A (en) * 1979-05-18 1980-11-29 Fujitsu Ltd Manufacture of semiconductor device
US4373965A (en) * 1980-12-22 1983-02-15 Ncr Corporation Suppression of parasitic sidewall transistors in locos structures
US4381956A (en) * 1981-04-06 1983-05-03 Motorola, Inc. Self-aligned buried channel fabrication process
US4547793A (en) * 1983-12-27 1985-10-15 International Business Machines Corporation Trench-defined semiconductor structure
JPS61226942A (ja) * 1985-04-01 1986-10-08 Matsushita Electronics Corp 半導体集積回路の素子間分離方法
IT1225636B (it) * 1988-12-15 1990-11-22 Sgs Thomson Microelectronics Metodo di scavo con profilo di fondo arrotondato per strutture di isolamento incassate nel silicio
US5681776A (en) * 1994-03-15 1997-10-28 National Semiconductor Corporation Planar selective field oxide isolation process using SEG/ELO
JPH1051065A (ja) * 1996-08-02 1998-02-20 Matsushita Electron Corp 半導体レーザ装置
US6900091B2 (en) * 2002-08-14 2005-05-31 Advanced Analogic Technologies, Inc. Isolated complementary MOS devices in epi-less substrate
US20060108641A1 (en) * 2004-11-19 2006-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Device having a laterally graded well structure and a method for its manufacture

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2098321A1 (enExample) * 1970-07-10 1972-03-10 Philips Nv

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6906939A (enExample) * 1969-05-06 1970-11-10
NL169936C (nl) * 1970-07-10 1982-09-01 Philips Nv Halfgeleiderinrichting omvattende een halfgeleiderlichaam met een althans ten dele in het halfgeleiderlichaam verzonken oxydepatroon.
NL169121C (nl) * 1970-07-10 1982-06-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon.
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
US3748187A (en) * 1971-08-03 1973-07-24 Hughes Aircraft Co Self-registered doped layer for preventing field inversion in mis circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2098321A1 (enExample) * 1970-07-10 1972-03-10 Philips Nv

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0236632A3 (en) * 1986-03-03 1988-10-05 Trw Inc. Formation of diffused buried layers

Also Published As

Publication number Publication date
US3891469A (en) 1975-06-24
JPS4958792A (enExample) 1974-06-07
NL7313681A (enExample) 1974-04-08
DE2349951A1 (de) 1974-05-02
FR2202368B1 (enExample) 1977-09-16
GB1436784A (en) 1976-05-26
JPS5228550B2 (enExample) 1977-07-27

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Legal Events

Date Code Title Description
ST Notification of lapse