FR2183709A1 - Semiconductor resistance - in epitaxial layer buried below insulating layer, for high element density - Google Patents
Semiconductor resistance - in epitaxial layer buried below insulating layer, for high element densityInfo
- Publication number
- FR2183709A1 FR2183709A1 FR7313782A FR7313782A FR2183709A1 FR 2183709 A1 FR2183709 A1 FR 2183709A1 FR 7313782 A FR7313782 A FR 7313782A FR 7313782 A FR7313782 A FR 7313782A FR 2183709 A1 FR2183709 A1 FR 2183709A1
- Authority
- FR
- France
- Prior art keywords
- epitaxial layer
- element density
- high element
- resistance
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US25244572A | 1972-05-11 | 1972-05-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2183709A1 true FR2183709A1 (en) | 1973-12-21 |
FR2183709B1 FR2183709B1 (US06262066-20010717-C00315.png) | 1976-05-28 |
Family
ID=22956030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7313782A Granted FR2183709A1 (en) | 1972-05-11 | 1973-03-30 | Semiconductor resistance - in epitaxial layer buried below insulating layer, for high element density |
Country Status (5)
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5112779A (en) * | 1974-07-23 | 1976-01-31 | Tokyo Shibaura Electric Co | Handotaisochito sonoseizohoho |
JPS52146578A (en) * | 1976-05-28 | 1977-12-06 | Texas Instruments Inc | Method of producing resistance element and semiconductor device having same element |
JPS54136279A (en) * | 1978-04-14 | 1979-10-23 | Nec Corp | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1547292A (fr) * | 1966-12-19 | 1968-11-22 | Gen Electric | Perfectionnements aux dispositifs à semiconducteur |
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
FR2098319A1 (US06262066-20010717-C00315.png) * | 1970-07-10 | 1972-03-10 | Philips Nv |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3404321A (en) * | 1963-01-29 | 1968-10-01 | Nippon Electric Co | Transistor body enclosing a submerged integrated resistor |
-
1973
- 1973-02-16 IT IT2047373A patent/IT979178B/it active
- 1973-03-24 DE DE19732314747 patent/DE2314747A1/de active Pending
- 1973-03-30 FR FR7313782A patent/FR2183709A1/fr active Granted
- 1973-04-11 JP JP4052673A patent/JPS5317394B2/ja not_active Expired
- 1973-04-13 CA CA169,267A patent/CA985793A/en not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1547292A (fr) * | 1966-12-19 | 1968-11-22 | Gen Electric | Perfectionnements aux dispositifs à semiconducteur |
FR2098319A1 (US06262066-20010717-C00315.png) * | 1970-07-10 | 1972-03-10 | Philips Nv | |
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
Also Published As
Publication number | Publication date |
---|---|
JPS4924373A (US06262066-20010717-C00315.png) | 1974-03-04 |
FR2183709B1 (US06262066-20010717-C00315.png) | 1976-05-28 |
CA985793A (en) | 1976-03-16 |
IT979178B (it) | 1974-09-30 |
DE2314747A1 (de) | 1973-11-22 |
JPS5317394B2 (US06262066-20010717-C00315.png) | 1978-06-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |