FR2139435A5 - - Google Patents

Abstract

1380983 Data processing system SIEMENS AG 8 May 1972 [12 May 1971 30 June 1971] 21307/72 Heading G4A A data processing system includes a data processor through which operands are passed in parallel by bit for processing, the processor being divided into two sections and arranged such that operands or parts thereof are fed in parallel by bit through both sections where they are subjected to identical processing and such that the processing results from the two sections are compared in order to indicate the presence of a fault. As described the processor is a 32-bit parallel device. Operands may be half width, 16 bits, or full width, 32 bits. Several modes of operation are described. In the first, with half width operands, the operands are fed through both sections of the processor, the processed results being compared to indicate the presence of faults. In the second, with full width operands, the operands are divided into more and less significant portions which are stored in separate sections of the store As. The less significant portions of two operands A and B, AL and BL, are fed in parallel through the two sections of the processor which comprise registers RS1 and RS2, processing units VE1 and VE2, and output registers ZSP1, ZSP2, a comparator VG serving to compare the processed results. The results are then stored in the store As and a similar procedure adopted for the more significant portions AH and BH. The processing unit has a carry input U which adds carries resulting from the processing of the less significant portion into the more significant portions. If the comparator indicates that no faults have occurred a full width operand is fed through the processing unit, now acting as a single section. In a further mode the test may be completed using only the less significant portion of the operands after which a full width operand is processed. In a further mode of operation in which a full width operand is processed in two halves, the results of processing the two halves are accumulated in the store As so that the test cycle also serves as the processing cycle. All modes of operation may involve several comparators, e.g. placed before and after each unit so that the precise location of the fault may be determined. Storage of the results may be overlapped with the supply of the next operands or operand parts to save time. The Specification states that the processor may be divided into other than only two sections with the appropriate comparators.