FR2078801A5 - - Google Patents

Info

Publication number
FR2078801A5
FR2078801A5 FR7105626A FR7105626A FR2078801A5 FR 2078801 A5 FR2078801 A5 FR 2078801A5 FR 7105626 A FR7105626 A FR 7105626A FR 7105626 A FR7105626 A FR 7105626A FR 2078801 A5 FR2078801 A5 FR 2078801A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7105626A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Application granted granted Critical
Publication of FR2078801A5 publication Critical patent/FR2078801A5/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR7105626A 1970-02-18 1971-02-18 Expired FR2078801A5 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2007353A DE2007353C3 (de) 1970-02-18 1970-02-18 Vierteiliges Addierwerk

Publications (1)

Publication Number Publication Date
FR2078801A5 true FR2078801A5 (fr) 1971-11-05

Family

ID=5762586

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7105626A Expired FR2078801A5 (fr) 1970-02-18 1971-02-18

Country Status (4)

Country Link
US (1) US3700875A (fr)
DE (1) DE2007353C3 (fr)
FR (1) FR2078801A5 (fr)
NL (1) NL7102179A (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1006982A (en) * 1972-07-10 1977-03-15 Tokyo Shibaura Electric Company Full adder and subtractor circuit
US3805045A (en) * 1972-10-30 1974-04-16 Amdahl Corp Binary carry lookahead adder using redundancy terms
US3814925A (en) * 1972-10-30 1974-06-04 Amdahl Corp Dual output adder and method of addition for concurrently forming the differences a{31 b and b{31 a
US3925652A (en) * 1975-03-26 1975-12-09 Honeywell Inf Systems Current mode carry look-ahead array
US3925651A (en) * 1975-03-26 1975-12-09 Honeywell Inf Systems Current mode arithmetic logic array
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
US4099248A (en) * 1977-01-28 1978-07-04 Sperry Rand Corporation One's complement subtractive arithmetic unit utilizing two's complement arithmetic circuits
US4084254A (en) * 1977-04-28 1978-04-11 International Business Machines Corporation Divider using carry save adder with nonperforming lookahead
US4163211A (en) * 1978-04-17 1979-07-31 Fujitsu Limited Tree-type combinatorial logic circuit
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4545028A (en) * 1982-10-13 1985-10-01 Hewlett-Packard Company Partial product accumulation in high performance multipliers
US4677584A (en) * 1983-11-30 1987-06-30 Texas Instruments Incorporated Data processing system with an arithmetic logic unit having improved carry look ahead
JPS60134932A (ja) * 1983-12-24 1985-07-18 Toshiba Corp プリチヤ−ジ型の桁上げ連鎖加算回路
US4660165A (en) * 1984-04-03 1987-04-21 Trw Inc. Pyramid carry adder circuit
DE3524797A1 (de) * 1985-07-11 1987-01-22 Siemens Ag Anordnung zur bitparallelen addition von binaerzahlen
EP0344226B1 (fr) * 1987-08-25 1993-05-05 Hughes Aircraft Company Systeme additionneur rapide
US4905180A (en) * 1988-12-16 1990-02-27 Intel Corporation MOS adder with minimum pass gates in carry line
US5097436A (en) * 1990-01-09 1992-03-17 Digital Equipment Corporation High performance adder using carry predictions
US5508952A (en) * 1993-10-19 1996-04-16 Kantabutra; Vitit Carry-lookahead/carry-select binary adder
US5619442A (en) * 1995-04-07 1997-04-08 National Semiconductor Corporation Alternating polarity carry look ahead adder circuit
US6076098A (en) * 1996-10-18 2000-06-13 Samsung Electronics Co., Ltd. Adder for generating sum and sum plus one in parallel
US6134576A (en) * 1998-04-30 2000-10-17 Mentor Graphics Corporation Parallel adder with independent odd and even sum bit generation cells

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL213922A (fr) * 1957-01-22
US2966305A (en) * 1957-08-16 1960-12-27 Ibm Simultaneous carry adder
US3105897A (en) * 1959-02-10 1963-10-01 Philips Corp Binary parallel adder utilizing sequential and simultaneous carry generation
US3202806A (en) * 1961-07-12 1965-08-24 Bell Telephone Labor Inc Digital parallel function generator

Also Published As

Publication number Publication date
DE2007353C3 (de) 1973-11-29
DE2007353A1 (de) 1971-09-16
NL7102179A (fr) 1971-08-20
US3700875A (en) 1972-10-24
DE2007353B2 (de) 1973-03-08

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Legal Events

Date Code Title Description
ST Notification of lapse