FR2035226A5 - - Google Patents
Info
- Publication number
- FR2035226A5 FR2035226A5 FR7004466A FR7004466A FR2035226A5 FR 2035226 A5 FR2035226 A5 FR 2035226A5 FR 7004466 A FR7004466 A FR 7004466A FR 7004466 A FR7004466 A FR 7004466A FR 2035226 A5 FR2035226 A5 FR 2035226A5
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
- G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Communication Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT5055969 | 1969-02-12 | ||
IT854659 | 1969-02-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2035226A5 true FR2035226A5 (fr) | 1970-12-18 |
Family
ID=53275923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7004466A Expired FR2035226A5 (fr) | 1969-02-12 | 1970-02-09 |
Country Status (4)
Country | Link |
---|---|
US (1) | US3641508A (fr) |
DE (1) | DE2004762A1 (fr) |
FR (1) | FR2035226A5 (fr) |
GB (1) | GB1296966A (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3824551A (en) * | 1972-05-18 | 1974-07-16 | Little Inc A | Releasable buffer memory for data processor |
US4001787A (en) * | 1972-07-17 | 1977-01-04 | International Business Machines Corporation | Data processor for pattern recognition and the like |
US3959777A (en) * | 1972-07-17 | 1976-05-25 | International Business Machines Corporation | Data processor for pattern recognition and the like |
FR2291545A1 (fr) * | 1974-02-20 | 1976-06-11 | Honeywell Bull Soc Ind | Dispositif de commande de transferts de donnees entre des unites centrales de traitement |
US5010479A (en) * | 1983-05-26 | 1991-04-23 | Hitachi, Ltd. | Information processing and storage system with signal transmission loop line |
US4881196A (en) * | 1985-02-19 | 1989-11-14 | Mitsubishi Denki Kabushiki Kaisha | Data transmission line branching system |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL299950A (fr) * | 1962-12-03 | |||
US3273131A (en) * | 1963-12-31 | 1966-09-13 | Ibm | Queue reducing memory |
US3304418A (en) * | 1964-03-02 | 1967-02-14 | Olivetti & Co Spa | Binary-coded decimal adder with radix correction |
US3337854A (en) * | 1964-07-08 | 1967-08-22 | Control Data Corp | Multi-processor using the principle of time-sharing |
US3351917A (en) * | 1965-02-05 | 1967-11-07 | Burroughs Corp | Information storage and retrieval system having a dynamic memory device |
US3414887A (en) * | 1965-12-06 | 1968-12-03 | Scantlin Electronics Inc | Memory transfer between magnetic tape and delay line |
US3411142A (en) * | 1965-12-27 | 1968-11-12 | Honeywell Inc | Buffer storage system |
DE1524545A1 (de) * | 1966-04-02 | 1970-09-17 | Telefunken Patent | Nullen-Wiedergabe bei Rechenmaschinen |
US3491341A (en) * | 1966-11-01 | 1970-01-20 | Minnesota Mining & Mfg | Recording system |
-
1969
- 1969-12-31 US US889758A patent/US3641508A/en not_active Expired - Lifetime
-
1970
- 1970-01-23 GB GB1296966D patent/GB1296966A/en not_active Expired
- 1970-01-29 DE DE19702004762 patent/DE2004762A1/de active Pending
- 1970-02-09 FR FR7004466A patent/FR2035226A5/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2004762A1 (de) | 1970-09-03 |
GB1296966A (fr) | 1972-11-22 |
US3641508A (en) | 1972-02-08 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |