FR1260009A - Circuit électrique d'addition ou de soustraction - Google Patents

Circuit électrique d'addition ou de soustraction

Info

Publication number
FR1260009A
FR1260009A FR810953A FR810953A FR1260009A FR 1260009 A FR1260009 A FR 1260009A FR 810953 A FR810953 A FR 810953A FR 810953 A FR810953 A FR 810953A FR 1260009 A FR1260009 A FR 1260009A
Authority
FR
France
Prior art keywords
subtraction
addition
electric circuit
electric
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR810953A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR1260009A publication Critical patent/FR1260009A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4912—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/383—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
    • G06F7/386—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements decimal, radix 20 or 12
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
    • G06F2207/4914—Using 2-out-of-5 code, i.e. binary coded decimal representation with digit weight of 2, 4, 2 and 1 respectively

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
FR810953A 1958-11-24 1959-11-23 Circuit électrique d'addition ou de soustraction Expired FR1260009A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH6655458A CH371279A (de) 1958-11-24 1958-11-24 Additions- oder Subtraktionsschaltung

Publications (1)

Publication Number Publication Date
FR1260009A true FR1260009A (fr) 1961-05-05

Family

ID=4527253

Family Applications (1)

Application Number Title Priority Date Filing Date
FR810953A Expired FR1260009A (fr) 1958-11-24 1959-11-23 Circuit électrique d'addition ou de soustraction

Country Status (4)

Country Link
US (1) US3055587A (fr)
CH (1) CH371279A (fr)
DE (1) DE1127634B (fr)
FR (1) FR1260009A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1286788B (de) * 1964-08-03 1969-01-09 Siemens Ag Anordnung zur Verringerung der Rechenzeit fuer die Differenzbildung zwischen zwei in je einer Zaehlkette gespeicherten Zahlen
DE1234055B (de) * 1964-11-05 1967-02-09 Ibm Deutschland Anordnung zur Addition oder Subtraktion
US3676658A (en) * 1969-12-12 1972-07-11 Singer Co Serial adder/substracter utilizing counters

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2803401A (en) * 1950-10-10 1957-08-20 Hughes Aircraft Co Arithmetic units for digital computers
US2654080A (en) * 1952-06-19 1953-09-29 Transducer Corp Magnetic memory storage circuits and apparatus
NL200526A (fr) * 1954-04-02
US2859359A (en) * 1956-01-31 1958-11-04 Sperry Rand Corp Magnetic binary counting circuit

Also Published As

Publication number Publication date
US3055587A (en) 1962-09-25
DE1127634B (de) 1962-04-12
CH371279A (de) 1963-08-15

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