FR1214950A - Circuit arithmétique - Google Patents

Circuit arithmétique

Info

Publication number
FR1214950A
FR1214950A FR776516A FR776516A FR1214950A FR 1214950 A FR1214950 A FR 1214950A FR 776516 A FR776516 A FR 776516A FR 776516 A FR776516 A FR 776516A FR 1214950 A FR1214950 A FR 1214950A
Authority
FR
France
Prior art keywords
arithmetic circuit
arithmetic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR776516A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR1214950A publication Critical patent/FR1214950A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4912—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
    • G06F2207/49195—Using pure decimal representation, e.g. 10-valued voltage signal, 1-out-of-10 code

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Error Detection And Correction (AREA)
FR776516A 1957-10-15 1958-10-13 Circuit arithmétique Expired FR1214950A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69035957A 1957-10-15 1957-10-15
US737043A US3070305A (en) 1957-10-15 1958-05-22 Serial delay line adder

Publications (1)

Publication Number Publication Date
FR1214950A true FR1214950A (fr) 1960-04-12

Family

ID=27104582

Family Applications (1)

Application Number Title Priority Date Filing Date
FR776516A Expired FR1214950A (fr) 1957-10-15 1958-10-13 Circuit arithmétique

Country Status (6)

Country Link
US (1) US3070305A (fr)
DE (2) DE1088259B (fr)
FR (1) FR1214950A (fr)
GB (2) GB884488A (fr)
NL (2) NL239382A (fr)
SE (1) SE301558B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7451049B2 (en) * 2004-02-27 2008-11-11 National Instruments Corporation Automatic delays for alignment of signals

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL143142B (nl) * 1947-02-26 Ford Motor Co Werkwijze en inrichting voor het bekleden van een elektrisch geleidend voorwerp, alsmede voorwerp bekleed volgens deze werkwijze of met behulp van deze inrichting.
US2931572A (en) * 1948-10-01 1960-04-05 Dirks Gerhard Decimal adder-subtractor device utilizing magnetic recordings
FR1010220A (fr) * 1950-01-28 1952-06-09 Soicete D Electronique Et D Au Convertisseurs de numération
GB747712A (en) * 1950-03-28 1956-04-11 Elliott Brothers London Ltd Improvements in digital calculating machines
US2787416A (en) * 1951-10-23 1957-04-02 Hughes Aircraft Co Electrical calculating machines
NL187428B (nl) * 1953-05-13 Cables De Lyon Geoffroy Delore Inrichting voor het vervaardigen van een beschermingsmantel van een optische vezel.
FR1085895A (fr) * 1953-06-04 1955-02-08 Méthode de soustraction et ensemble soustracteur pour nombres en impulsions codées
FR1086043A (fr) * 1953-07-02 1955-02-09 Electronique & Automatisme Sa Perfectionnements aux multiplieurs pour calculatrices électriques numériques
US2869786A (en) * 1956-04-17 1959-01-20 David H Jacobsohn Adder circuit

Also Published As

Publication number Publication date
GB888537A (en) 1962-01-31
SE301558B (fr) 1968-06-10
US3070305A (en) 1962-12-25
GB884488A (en) 1961-12-13
DE1088259B (de) 1960-09-01
NL232224A (fr)
NL239382A (fr)
DE1105203B (de) 1961-04-20

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