FI96373B - TST architecture expanded with buses - Google Patents

Description

The present invention relates to a TST architecture according to the preamble of claim 1 in digital cross connect (DXC) for implementing general distribution or route authentication, and to cross-routing general algorithms, in particular cross-routing algorithms.

Recommendations CCITT G.707 defines the signals of the first level Synchronous Transport Module (STM-1) of SDH signals. Other defined levels are STM-4 and STM-16. Recommendations CCITT G.708 define the frame structure STM-N (where N = 1, 4, 16). In the STM-1 frame, 63 subsystem containers can be transferred (e.g., TU-12, Tributary Unit, which may contain a standard 30-channel PCM system 2 Mbit / s signal). The STM-N frames are assembled from several STM-1 signals, e.g. the STM-4 signal consists of four STM-1 signals.

Digital cross-connect systems, 15 CCITT draft recommendations G.sdxc-1 ...- 3 have been defined for SDH. SDH DXC is defined (freely abbreviated): A digital SDH cross-connect device is an Rk device with two or more interfaces at SDH speeds (G.707) and capable of at least termination of the transfer section and controlled, transparent switching and reconnection of virtual containers (VCs). between the connection ports.

20 SDH The DXC can transmit traffic between different SDH levels as well as connect traffic differently. between signals. The use of cross-connection also involves the possibility of remote control of routing, route verification, introduction of backup routes, switching from one signal to many signals (universal distribution), etc. Usually the connections are two-way.

25 Cross-connections can be implemented with many architectures. Known are TS-ra-; kenne (Time-Space) and the TST structure (Time-Space-Time), i.e. a time-space-time cross-field that quite well satisfies the conditions of non-blockability and feasibility. TST cross-connection is also suitable for very large cross-switches, although this causes some problems as the system expands.

The architecture proposed in the invention can be considered as an intermediate form of T ^ S and TST architectures. In the T ^ S architecture, the first step is the T-switches arranged in a square, and it is known that it is unobstructed, but also expensive. Some DXC manufacturers use the T ^ S architecture. There are problems with the TST structure when using SDH standard route authentication (Sub Network Connection Protection), and especially in Broadcasting.

To solve the above problems, the present invention proposes an n (TS) T-5 architecture characterized by the features of claim 1. Simply put, the proposed architecture uses the TST architecture for routing, and the parallel TS structure for general distribution, whereby the parallel TS stages are connected to the basic TS stage by means of input and output buses. In the general notation n (TS) T, the letter n means the guaranteed number of parallel outputs of the general distribution. In fact, the architecture of the present invention combines the affordability of TST with the freedom to choose T ^ Srn connections. The architecture according to the invention can be implemented with an architecture of a reasonable scope.

According to preferred embodiments of the invention, the S-stages of the proposed architecture are extended in the form of a full Benes network for larger digital cross-connect capacities. Alternatively, the expansion is done in the form of a reduced Benes network, so that the universal distribution can be solved more cheaply than in the case of a full Benes network. The reduced network is based on the use of a special reduction bus.

In the architecture according to the invention, n (TS) T routing, including general distribution routing, 20 can be handled by a simple algorithm. For the user, this architecture provides unobstructed normal routing through the cross-connect, in addition to unobstructed broadcast 1 -> n. Route backup (Sub Network Connection Protection) can be considered a special case of broadcast, where n = 2. The maximum branch branch 1 -> x depends on the number of parallel TS stages . Correspondingly, the route verification selection (2-> 1) can be made on the receiving side so that the selected signal can be freely routed by means of S-switches.

The structure according to the invention can advantageously be implemented by means of modular integrated circuits, e.g. so that the same card has one T-switch stage containing: 16 time switches for STM-1 signals and one state switch 16 * 16 for STM-1 signals. for foxes.

The invention will now be described in more detail by means of direct examples and with reference to the accompanying drawing, in which: Figure 1 shows a basic block diagram of an n (TS) T architecture according to the invention; 3 96373 in Fig. 2 an embodiment of an n (TS) T-architecture routing algorithm is considered by means of a diagram when n = 3; Figure 3 illustrates the problem situation in the n (TS) T architecture when n = 2; Figure 4 shows an embodiment of an n (TS) T architecture of the form 32 * 32 with n = 2; Figure 5 shows an embodiment of an n (TS) T architecture applying a reduced S-stage extension for general distribution; Figure 6 shows an embodiment of an n (TS) T architecture applying a fully reduced expansion of the S-stage 10 for general distribution; Figure 7 schematically illustrates a routing algorithm for a reduced n (TS) T architecture in parallel TS stages for general distribution when n = 3; and Figure 8 shows the number of chips with different parameter values and in different reduction cases as comparison tables.

15 Figure 1 shows a basic block diagram of the n (TS) T architecture. It can be seen from the figure that this architecture is based on a conventional TST architecture, in which the basic TS stage 121, 131 is extended by parallel TS stages 12n, 13n connected in parallel. The expansion takes place by means of two buses, the input bus IB being between the first T-stage 12 of the input terminal Ilja and the output bus 20 OB (output bus) between the S-stage 13 and the last T-stage 14. The T-stage 14 is then connected to the output terminal 15.

In Figure 1, the TST stage 121, 131, 14 of the top row implements normal routing through the switch. General distributions are implemented on the TS stages 12n, 13n of the extension. The universal distribution operates in such a way that the input bus IB "copies" the signals from the input terminal 11 to all the TS stages 12. From the second, third, etc. TS stage 122, 132; : * 123, 133; ... the desired universal distribution signals can be selected individually, because only one signal from the distribution signal is connected via the TS stage. This is actually the normal operation of the TST switch.

In the T-architecture of Figure 1, the routing of normal point-to-point connections and one single broadcast signal can be implemented by something known per se. TST algorithm. If from the second, third, ..., th TS parallel stage 122, 132; 123, 133; ... routing signals must be routed, so due to the TST algorithm 4 96373 min, there are empty time slots on the output bus OB. The universal distribution algorithm must route the universal distribution signals to these empty time slots of the TS stages. Considering the routing of a particular broadcast signal 1 -> x, where x is the degree of universal distribution, some (n-1) TS stage option is available for it. Fig. 2 shows 5 n (TS) T as an example, where n = 3 and considering the connection of signals from the input bus IB through the TS stages 12 to the output bus OB (in Fig. 2 the notation T and Output refers to the last T-stage 14 and output terminal 15 not shown). Thus, in the example of Figure 2, the size of the DXC is only 4 * 4 for clarity and there are only 4 time slots. In this example, the success of the general distribution 1 -> 3 is guaranteed when n 10 = x = 3. The numbers in the boxes indicate the desired output port 1 ... 4. By means of the basic TS stage 121, 131, after the state switch 13, the output to the bus OB is provided with the free slots shown on the shaded screen in the figure, to which the signals from the parallel TS stages can be adapted as shown.

However, TS routing encounters a discrepancy because there can be 15 multiple broadcast signals on the same input of the TS stage. This situation is illustrated in Figure 3, where, for simplicity, the situation of n (TS) T is considered when n = 2. The conflict situation is shown on the left side of the figure, where universal distribution signals are routed from input bus IB to second line, i.e. to second input. If more than one universal distribution signal tends to the same output bus OB slot via the S-switch 13 20, a blocking situation arises. The blocking situation is due to the nature of TST routing, as the result of TST routing could set the available empty slots in the same time slot. In the worst case, all empty spaces are in the same time slot. It should be noted, however, that a conflict situation arises when signals compete at the same TS stage, and not from competition between signals at different TS stages. To avoid block 25, information about a possible conflict situation in the TS routing result must be passed to the TST algorithm. This means that in these cases, the TST and TS routing algorithms must be executed recursively again until an acceptable solution is found. Thus, it is found that the routing of the general distribution is preferably done in two stages, first for the parallel TS stages and then for the whole TST.

; : 30 Recursively implementing different parts of the routing will result in the execution of the Hita bog.

As a result, the TST algorithm can be developed to take into account the requirements of TS routing. In this case, the final n (TS) T algorithm in a one-time operation solves the configuration without inhibition. A suitable universal distribution stage x can be found without an expensive hardware solution, as is the case with the T2S architecture s s a.

35 In principle, n (TS) In a T-architecture, the number n of parallel steps indicates the guaranteed overall distribution rate. However, the algorithm can be developed so that the 5 96373 universal distribution rate it gives is greater than n. In this case, however, there is in principle a probability of blocking, because routing through a universal distribution rate exceeding the guaranteed universal distribution rate (= n) is not possible in all cases. Routing with an "oversized" universal distribution rate requires significantly more execution time than a simple 5 routing algorithm. One way to implement "oversized" broadcasting unimpeded is to perform n-degree redundancy in the TS distribution stages by amplifying the broadcast signal at the time switches. Thus, TST routing is not disturbed. TS distribution stages implement gap replenishment for all "oversized" distribution signals. Unobstructedness is obvious if sufficient amplification capacity is found in the time switch of the distribution stages.

10 Route verification is implemented on the output side so that the signal to be verified is amplified into two signals (W, P, Working, Protecting) and routed in the same way as in the case of universal distribution. The implementation of the route verification on the receiving side is done in such a way that both verification signals (W, P) are applied to a different TS stage. The verified signal (W) is applied to the first TS stage, 121 and 131 in Fig. 15 1, and the verifying signal (P) is applied to n TS stages, 12n and 13n in Fig. 1. Both signals are routed to the same port in the same time slot. The S-switches select the signal to be switched.

A possible application of DXC has been discussed above, in which, for example, 20 16 * 16 modules can now be easily implemented on the same card or integrated circuit, i.e. on a chip. If larger units are required, e.g., 128 * 128 or 256 * 256, there is a common S-stage expansion problem in all architectures when extending n (TS) T. The chip unit could potentially be expanded, but said large sizes do not currently make sense as a single chip solution, in which case the only-. Another option is a network solution. The Benes solution, which requires as few resources as possible to expand the switch stage, is the least costly and still enables an unobstructed solution for the S stage. The number of T-steps increases linearly as the DXC increases.

The Benes solution means that each S-switch of n (TS) T must be implemented as a complete Benes network. In this case, each broadcast stage (TS) can route 30 broadcast signals to any desired time slot. Figure 4 shows the principle of this solution, taking as an example an architecture that has been extended to size 32 * 32 and where n = 2. The state switches 13 (S) have the form 16 * 16 and there are 8 time switches 12 (T). In each state stage, there is a connection from each state switch 13S1, 13S2 to each subsequent state switch 13S2 and 13S3, respectively.

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However, the full implementation of the Benes network will be costly. Therefore, it is preferred to reduce the Benes network so that the number of chips can be reduced. The reduction then means that the number of universal distribution stages (TS) is minimized and a reduction bus RB (reduction bus) is introduced, with which the outputs of the middle status switches 13S2 of the universal distribution stages 5 are connected in parallel to the last switches 13S3 in the status report. Two different reductions can be used: the overall distribution ratio reduction in Figure 4 and the complete reduction in Figure 5.

Reducing general distribution only applies to general distribution steps. The last S-stage of the complete Benes network, S3 in Figure 5, is fully utilized. S3 performs the same operation for all TS stages, whereby S3 switches the signals connected to it to the desired output. Thus, only one group of S3 switches is required for all universal distribution stages. The reduced network is unblocked because the maximum number of signals in a time slot, N, can be connected by only one S3 subgroup. The reduced Benes network is amplified, and up to N signals can be routed to any output of the reduced Benes-15 network. Thus, there is no blocking in the routing of the universal distribution path as long as the degree of universal distribution x is less than or equal to the number of available parallel TS stages, n> x. In the example of Figure 5, N = 32 and n = 3. The last T-stage is not shown in Figure 5. In the same way as in Figure 4, the mode switches are of size 16 * 16.

20 The reduction can also be carried out completely, as already mentioned. In this case, the output bus OB and the S3 subgroup common to the general distribution can be omitted. The reduction bus RB is then connected directly between the second state stage S2 and the third state stage S3 of the Benes network. Figure 6 shows the principle of full reduction, where N = 32. and n = 3. The last T-step in Figure 6 is not shown.

25 The basic problem of configuration remains the same: empty spaces still occur in the same time slot, but possibly in a different "output" As in the case of the above solutions. The last state stage (S3) of the Benes network of the TST part simply performs signal switching to the address output, i.e. performs the last reordering. Prior to the mode switches S3, empty slots of up to N in the same time slot can be accessed through the output slots of the reduced Benes network having the same number. The amplified Benes network allows universal distribution signals (up to N in the same time slot) to access these outputs of the Benes network regardless of the signal source. By placing the empty spaces from the TS stage in the correct way, routing conflicts that would cause blocking can be completely avoided.

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The following is a closer look at the routing algorithm of the Benes network. For the normal Benes network shown in Figure 4, the algorithm is basically similar to that already explained in connection with Figures 2 and 3. However, the extension of the state-of-the-art Benes-Veiko complicates the situation, as the algorithm needs to be developed to include routing over the Benes network. Routing per se is not cumbersome, but its extent slows down performance.

The algorithms for reduced architectures are different from those for a normal architecture. The main differences between the three algorithms of the cases described above are how much the TST and TS routings or the routings of the different TS stages are interdependent. Normal Benes architecture has the loudest interdependence, i.e., TST and TS routing can be done mainly independently of each other. On the other hand, a fully reduced architecture has the most rigid dependence, i.e., there is a rather strong dependence between TST routing and the routing of different TS stages.

The stronger the constraints the architecture places, the more complex and slower the algorithm becomes. The reduced architecture of the general distribution has the same loose dependence between the TST and TS stages as the normal Benes architecture, but the algorithm is more complicated because there is a more rigid dependence between the TS stages.

The reduced general distribution differs from the routing of a normal complete Benes network for routing through 20 state stages. Since the Benes network is reduced, all universal distribution signals must be connected via the same reduction bus RB. There is no capacity problem for bus RB, because a maximum of N signals must be routed through the bus N bus. However, routing is not as free as in the normal Benes-t case, where individual routing can be performed at each TS stage. When using a reduction bus, all universal distribution stages must be routed, ie processed in the same work step. The normal Benes routing principle can be used, but the problem is broader.

Figure 7 shows an example of the routing of TS stages of a reduced architecture for general distribution when N = 8 and n = 3. In a perfectly reduced case, both 30 TST and TS stages must be considered together. Here, all signals use the RB reduction bus. This means that empty gaps must be left in the TST section in places where there is access to this bus from the TS stage. However, the routing of the Benes network in the TST stage is basically the same as in the reduced broadcast architecture above. In fact, the routing example of Figure 7 represents a complete; 35 reduced architecture when n = 2. The upper stage represents the TST stage.

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From Figure 7, the output bus OB can be removed and replaced by the last T-switch portal 14 to implement a completely reduced architecture. Figure 7 also illustrates how signals must be routed correctly at the S 1 switch stage to avoid collisions on the reduction bus; this example shows the signal assigned to output 2 5 and its incorrect and correct routing capability in the S1 switch.

One way to implement the "direct try" algorithm of a perfectly reduced case is to mark blank slots for a given broadcast signal before routing; this is shown in the reinforced screens at the output of the S3 stage. These empty signals are then routed normally through the TST stage 10, forming the target locations of the universal distribution signals on the reduction bus RB. The TS stages direct the universal distribution signals to these points. The posting of the blanks must, of course, take into account the inconsistencies of the TS routing and the general routing of the reduced Benes network of the universal distribution steps.

The following is a review of "oversized" distribution. The algo-15 rhythm of the "oversized" distribution level already faces difficulties in the normal Benes expansion. The Benes format S-switch does not allow free copying to the outputs. This is because the signals to be amplified overlap when trying to use the same network connection in a network of mode switches. But here, too, as before, it is a question of how well the action is made. The variables used in the optimization are N, n, traffic-20 load, Benes application, and extent of general distribution (1 -> x).

Next, the estimation of resources in the architecture according to the invention will be considered. The components of the example architecture are a T-switch with a length of 63, ie 63 time slots. The size of the state switch is 16 * 16. Each switch can be implemented with a single chip architecture, where the number of chips is:

25 a) Single chip: (n + 1) * N * T + n * S

In an extended architecture, the number of chips is:

b) Normal Benes network (Full Benes): (n + 1) * N * T + n * 3 * (N / 16) * S

c) Broadcasting rate reduced (Broadcast): (n + 1) * N * T + n * 2 + 2) * (N / 16) * S

d) All reduced: (n + l) * N * T + n * 2 + 1) * (N / 16) * S

30 The above figures can be compared to the T2S architecture (Sqr (T) S), where:

T2S: N2 * T + N * S

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Figure 8 shows the number of chips with different values of the parameters as comparison tables. It can be seen that the number of chips in the architecture according to the invention is reasonably small with a low distribution rate (smaller n) of the general distribution compared to the T ^ S architecture. In larger systems, i.e. N is large, the difference in favor of the architecture according to the invention is emphasized.

The way TS modules or chips and buses are implemented has a major impact on feasibility. The busbars are simple in structure, although the large size can cause problems. However, compared to many other architectures, e.g. the T ^ S structure, in the system according to the invention the bus is much easier to implement with n being small.

The number of signals in the TS routing section is relatively small: a maximum of half of the load can be routed through the TS stage when n = 2 and all signals are universal distribution signals (x = 2). In this case, the execution time is clearly shorter than the normal fully loaded execution time of the TST algorithm.

The n (TS) T architecture of the invention is highly modular with respect to the desired degree of general distribution. This modularity allows the DXC user to expand and / or modify their DXC hardware as needed. The architecture provides the desired universal distributions without blocking. The configuration algorithm is relatively straightforward and thus fast. As mentioned above, the architecture can preferably be expanded to a DXC size of 128 * 128. Going beyond this size, due to the size of the mode switch in the example, a simple Benes network is not enough, it still needs to be expanded.

: On the other hand, it can be seen from the above explanation that the general distribution steps are not used very efficiently, except at the "oversized" distribution level. With an excessive distribution level 25, the algorithm becomes complicated, resulting in longer execution time and / or blocking cases.

The n (TS) T architecture according to the invention uses parallel universal distribution stages, which makes it possible to implement universal distribution at the lowest possible cost; distribution algorithm processing. The biggest advantages of the presented architecture are obtained with small degrees of general distribution (x is small), because then the costs caused by the number (n) of parallel stairs can be better utilized for traffic handling.

There has been a way to verify SDH signals. Of course, other signals with a similar structure, such as PDH signals, can use the same authentication method.

Claims (9)

10 96373 1. In a digital cross-connect of broadcasting and / or path protection for the implementation of the TST architecture which comprises the signal lines input terminals and output terminals and between the input side of the time switches (T), space switches (S) and starting five-side time switches (T), characterized in that the input side of the time stage (12) and tilapor-in (13) formed in parallel with the basic TS series connection (TS) is coupled to one or more same time stages and space stages formed by the parallel TS series connections (TS), wherein the inlet (13) signals is connected to the input bus (IB) via the parallel inputs of the input side of all the time switches (121 ... 12n), and wherein the status of the switches 10 through (13) outputs signals are coupled to the output bus (OB) in parallel to the output side of the time switch (14) inputs (figure 1). TST architecture according to Claim 1, characterized in that the respective state stage (131 ... 13n) is extended in the form of a full Benes network, the extension being of the form state-state-state (S1-S2-S3) and in which each parallel TS series connection of the output 15 has access to the output side of the time switches (T) in each time slot (figure 4). TST architecture according to claim 1, characterized in that the state stage (13) is extended in the form of a reduced Benes network, so that in the basic TS series connection (121, 131) and in the first parallel TS series connection (122) , 20 132) the extension is in the form state-to-state (S1-S2-S3) and in other parallel TS serial connections the extension is in the form state-to-state (S1-S2), whereby the state stages of these latter parallel TS serial connections (S2) outputs of which are connected in parallel through a re-dusointiväylän (RB) of the first parallel TS series connection of the output side of the space stage (132 / S3) of inputs (figure 5). TST architecture according to claim 1, characterized in that the state stage (13) is extended in the form of a fully reduced Benes network, so that in the basic TS series connection (121, 131) the extension is in the form state-state-state (S1-S2). -S3) and in parallel, strip TS series connections (122 ... n, 132 ... n) the extension is in the form state-to-state (S1-S2), 11 where the outputs of the state stages (S2) of the parallel TS series connections are parallel NCP-30 through Ketty redusointiväylän the basic TS series connection of the output side of the space stage (131 / S3) of inputs (figure 6). An algorithm for routing a broadcast signal to x output slots in a digital cross-connect TST architecture according to claim 1 or 2, comprising • parallel n basic and parallel TS serial connections, wherein x <n, characterized in that n 96373 broadcast signals are copied from the basic and to the inputs of the time switches (12) of the parallel TS series connections, whereby the algorithm searches for free spaces in the output bus (OB) for the universal distribution signals (Fig. 2). Algorithm according to claim 5, characterized in that the total algorithm of TST routing 5 includes a separate sub-algorithm for TS routing, wherein feedback information is derived from the TS routing solution for the total TST algorithm and wherein TS routing is repeated with new parameters if TST part algorithm produces an inhibitory lumbar. The algorithm of claim 5, according to claim 3 10 in the TST architecture, characterized in that the algorithm solves all the routing of the TS serial connections (12, 13) as a common problem space (Figure 7). Algorithm according to claim 5 in the TST architecture according to claim 4, characterized in that the algorithm solves all the routing of the TS serial connections (12, 13) as well as the routing of the TST entity (12, 13, 14) as a common problem space. Algorithm according to Claim 8, characterized in that the algorithm first allocates the free spaces for the general distribution signals at the output of the state stage (13 / S3), after which the algorithm solves all routing of the TS serial connections (12, 13) and the TST entity (12, 13, 14). ) routing as a common problem space. 12 96373