FI97600C - Connection of SDH signals in a TS'S'TS'S'T switching field - Google Patents

Description

j 97600 Connecting SDH signals in the TS'S'TS'S'T switching network -Koppling av SDH-signaler i ett TS'S'TS'ST-copplingsfält

The invention relates to the use of a TS'S'TS'S'T switching network and in particular to a method for switching SDH STM-N signals.

The synchronous digital hierarchy (SDH) comprises a large set of time-division signals for transmission in a telecommunications network. Mention may be made of Recommendation ITU-T 5 G.707, which defines the STM-1 signal of SDH signals, i.e. the signal of the first level Synchronous Transport Module. Other defined levels are STM-4, STM-16, and STM-64. Recommendation ITU-T G.708 defines the STM-N frame structure (where N = 1, 4, 16, 64). The STM-1 basic frame consists of bytes (8 bits). In the STM-1 frame, 10 units of the subsystem can be transferred, e.g. 63 pcs. TU-12 signals, each of which can carry 2048 kbit / s signals. STM-N frames are assembled into logical superframes. SDH signals are generated from the signals of the subsystems by interleaving bytes. In this way, each signal can be separated into its own time slot in the main signal.

Digital Cross Connect systems (ITU-T 15 draft recommendations G.sdcx-1 ...- 3) have been defined for SDH. The SDH DXC is capable of connecting different SDH traffic levels as desired. The use of cross-connect devices involves the possibility of establishing remote routings, connecting traffic to alternate routes, connecting traffic from one signal to many signals (broadcasting, etc.) Usually, the connections through the cross-connect device are bidirectional.

There are many different types of cross-connect architectures. The structure that satisfies the conditions of unobstructedness and feasibility is the square time switch structure TxT S (Time x Time - Space) structure. As this time switch structure expands quadratically, in large cross-connect devices, the size of the hardware becomes very large.

25 In principle, time switches are memory elements and a state switch consists of switch elements.

::: Unobstructedness and feasibility are also met by the very double-capacity TST (Time - Space - Time) structure, i.e. the time-space-time cross-connect structure. The TST structure is better suited for large cross-connect devices than the TxT S structure, 30 because in the TST only the size of the state switch increases squarely. However, depending on how the mode switch is implemented, its size can become a problem in larger cross-connect devices.

2 97600 Such a problem can be solved by a modified state switch stage arrangement in which only the state switches are replaced by a switch network. When time connections are also possible in the switching network, the capacity of the outermost status switches can be simple. The middle switch block of the system is commonly referred to as T&S.

5 The T&S switch block may be, for example, in the form of space-time mode, STS, or time x time mode, TxT-S. Using the preferred structure, the middle stage STS structure, the entire switching network is then of the form TS'S'TS'S'T. In this case, the STS structure of the middle stage can advantageously have twice the number of inputs and outputs compared to the number of inputs and outputs of the entire switching network.

10 Each switching element must be able to switch signals on a byte-by-byte basis.

It is now an object of the invention to provide a method for switching SDH signals in a TS'S'TS'S'T switching network which can be used to implement non-blocking switching.

This object is solved by the method according to claim 1. Other preferred embodiments of the invention are set out in the dependent claims.

The presented task is solved by the method of the invention, in which the signals to be switched can be compressed so that new signals can be generated simply and quickly through the free parts of the switching network. Once the new connections have been made, the connections are packed so that at least the same number of free parts are available again.

The invention is essential that the signals are effectively arranged in the input side of the time. . toggle switch blocks. In this case, a solution is obtained for the signals that pass input side through the time and space switches to the time switch outputs of the same Al "in time slot is not more than one switching network at the same output port of the degree of signal 25 signals, and that the mode switches the outputs of the active center stage at the same center block does not go more than one be routed to the same output block signal, wherein the missing al-kakytkimissä and space switches in the previous steps the solution of the desired signals are passed through the center stage more blocks of the output side of the space-time switches.

:: ‘The method and cross-connect architecture of the invention can be used at all SDH levels, i.e. for cross-linking the defined signals STM-1 ... STM-64 and other similar signals. Although the accompanying figures start from a conventional mode switch module with 16 inputs and 16 outputs for AU-4 signals (= STM-1 capacity), it is natural that smaller and especially larger numbers of signal lines can be applied within the scope of the inventive idea.

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In a cross-connect network, it is essential that the connections can be made byte-by-byte. In this case, higher-level signals such as AU-4, TU-3, and TU-2 are "fragmentable" into as small portions as TU-12 signals. The method of the invention preferably first processes the AU-4 signals in the ports of the input stages, which are routed through the stages of the switch-5 so that they are in each case primarily routed through the space-time-space block of the same middle stage.

The switching algorithm does not seek to optimally compress signals through the second or active half blocks of the middle stage, as it has been found in practice that when a suitable algorithm is used and a solution is applied to the first time switch 10, usually only a few signals do not fit within the solution. The same applies to the first mode switch stage.

Several solution algorithms for the first state and time switch can be found. The solution for the state switch is to arrange the time slots so that after the switching arrangement, there are not more than 15 signals going to the same port in one vertical row, i.e. the time slot. If such a solution is not found, the signals breaking the correct solution are connected to the middle stage via additional blocks.

The corresponding algorithm used to find a solution for time switches can also be used for the first state switch stage. The aim here is to solve the situation in vertical rows, i.e. in time slots, so that no more than 20 several signals going to the same output block go to the same middle block. As in the time switch solution, when no solution is found, signals that violate the correct solution are connected to the extra blocks.

If the compression is to be made more efficient, the algorithm can be improved after the first retrieval of solutions by repeating the arrangement of the signals in the first 25 TS blocks. The object is to ensure that the central STS stairs, the number of the signals which go to an output side of the ST block • · * size must not exceed the number of time slots, which is 63. In addition, the input side of the TS-dragon-avenge STS block destined the number of signals cannot exceed the capacity of the AU-4 signals. If the compression capacity is to be enhanced in the manner mentioned above, the STS algorithm has to be solved in the middle stage blocks in order to get the signals out to the final stages in the correct order.

In practice, when solving the solutions for the time and mode switches separately, the compression is sufficient to have enough space for the new signals in the extra middle blocks before repackaging. In this case, the rest of the rhythm of the switching algorithm 35 implementing the method is also very simple. In the actual middle blocks, it is only necessary to make a state switch of 4 97600, which can only be done in one specified way. In the last ST blocks, the signals can also be switched in only one specified way so that the signals can be routed correctly. For AU-4 and TU-3 signals, the first 18 columns of the STM-1 frame must be processed separately. The same principles as mentioned above can be followed in the connection.

The invention will now be described by way of example with reference to the accompanying drawing, in which Figure 1 shows a 128-port digital crossover implemented with the TS'S'TS'S'T architecture; and Figure 2 shows, in a simplified manner, the notation of the signals of the switching network.

Figure 1 shows a TS'S'TS'ST switching network of AU-4 signals with 128 inputs and 128 outputs, in which the algorithm according to the invention is applied. In the figure, TSW stands for Time SWitch and SSW for Space SWitch.

The outermost switch arrangements in Figure 1 are substantially mirror images of each other. The Tar-15 is irrigated more closely on the input side (left in the figure) with 16 time switches TSW, each with 8 inputs and 8 outputs, which are connected to the first state switch stage SSW. Each mode switch has 8 inputs and 16 outputs, always one of which is routed to one of the status stages in the middle block.

In the middle blocks, the structure of the second mode switch is 16 * 16, and its outputs are connected to the ai-20 capacitor 16 * 16. (With respect to this middle time switch, the cross connect is symmetrical so that the output of the time switch 16 provides a total of 128 outputs). Central block output side mode switches the outputs derived from the output side in each case to each space switch. It is noted that in the example of Figure 1, the total capacity of the middle blocks is twice the capacity of the outermost blocks. Thus, in the middle blocks, i.e., the space-time-to-state switch blocks, it can be said that switch blocks 1 to 8 are active, and blocks 9 to 16 are additional blocks used to handle inhibit situations and generate new signals, which is discussed in more detail in the example below.

This TS'S'TS'ST architecture in Figure 1 is a modified reconfigurable • 30 Clos structure. In this case, "modified" means that the conventional TST architecture has been extended by: a) placing time and space stages in the middle of the switch, and b) adding 8 blocks to the middle stage. The first variant (a) eliminates the possibility of inhibition, or more precisely, in theory, inhibition is thus made very unlikely even without the second transformation. This small 35 probability is completely eliminated by the second transformation (b). Another variant j 97600 is needed primarily to speed up the operation of the TS'S'TS'ST switch, because in particularly difficult cases the solution of the TS'S'TS'ST algorithm may require a very long time, in practice 2 to 30 s with prior art devices. Normally, the additional blocks ensure that free channels are always available for new bidirectional signals. Once the signals are configured, the TS'S'TS'ST algorithm is resolved with eight empty blocks left again.

For the sake of explanation, Figure 2 shows a simplified example of the markings of the signals to be processed when the switching network has 3 input blocks, each with 3 input ports. Thus, there are nine input signals, and in the example of Figure 2, they have two time slots in operation. In the figure, two numbers are marked for each input signal, the first of which indicates the desired output port for the input signal, and the second indicates the desired time slot of the signal leaving the output port.

If two signals are going to the same time slot, these signals are copied to the outputs as a broadcast. For selection purposes, signal selections are required, indicated in Figure 2 by signal selection (6,1; 3,2). This means that there may be two input signals going into the time slot of the same output port. In this case, one of these signals is selected in the mode switch. The selected signals should be located on the same input block.

In the following, the method according to the invention will be examined in more detail. substantially invention 20 in the input side of the time and space switches, the signals are arranged so that one of the STS blocks SSW-TSW-SSW signals coming from the output of obey the rules: the STS block number of the signals which go to an output side of the ST-Iohkoon (SSW-TSW), no must not exceed the number of time slots, which is 63. In addition, the input side of the TS block destined STS block · .: 25 can not exceed the number of AU-4 signal capacity. Clean at the input ports: · The AU-4 signals must therefore be routed through the switch stages first to provide fast AU-4 signal connections. This means that they are most preferably routed through the same STS block.

Upstream of the space switches the signals output from the output ports are shown by the conditions: 30 signals are lead to a block of the center stage, that they can achieve the correct TS'S'TS'ST structure of the output side of the ST segment; and only one time slot may be applied to the same output port at a time. These terms are very simple and obvious. These can be used to find quite a few different options for outgoing signals. If the switching algorithm implementing the method is not able to find a suitable solution for any signal in the middle half of the active half

through, a central SSW-TSW-SSW must be used to establish the connection

6 97600 stage additional STS blocks. This means that in the architecture according to the invention, the algorithm according to the invention does not require difficult, computationally consuming recovery steps.

If there are several signals going to the same port in the vertical row, i.e. in the time slot, one or other signals can be routed through the additional blocks. According to the invention, the idea is to arrange the signals so that no more signals belonging to the same group can enter the same STS block than there are time slots in the block. The idea of row numbering in the tables below is thus that the signals applied to the same middle stage STS block have the same row numbers.

10 Upstream TS blocks of the output signals from the first arranged, so that the above conditions are met. TS'S'TS'ST this structure, the supply-side TS blocks do not provide a general transmission (broadcasting) signals, that is, copying, and therefore yleislä-broadcasts can not cause blocking in these blocks. Copies are most preferably made in the middle stage. The VC-12 signal this would be a result of hedges 15 causes corrosion, and this can be prevented by arranging, for example, the output signals again (repeating the arrangement several times) to the input side of the TS blocks, if inhibition seems to arise.

The TS blocks of the input stage are distributed to the blocks of the middle stage. According to Figure 1, the outputs of the input stage status switches are connected in each case so that the top output of 20 blocks is connected to the middle block, the second highest output to the second block of the middle stage, etc. Each middle stage block receives the outputs of the previous , the second input port of the second block of the second output, etc.

Since most broadcasts should be made in the middle stage STS blocks, they should find solutions for the outgoing signals such that the switching is unblocked. Erää-

• «I

this simple rule to avoid blocking could be that the same broadcast signals should be routed out of the STS blocks at the same time, i.e. at corresponding time slots. If, nevertheless, blocking occurs, the outgoing signals must be rearranged and this is repeated until a blocking connection is obtained.

"" · ". *** 30 of the center stage switching solutions are now relatively simple and suoraviivai costs because the input side of the time and space switches to the transmission of the arrangements in accordance with the invention. Thus, in practice, no time switching is required at the middle stage, but only state connections are made in the blocks, as shown in the signal arrangement example shown below with the help of Tables 1 to 8.

7 97 600 on the output side switch blocks SSW-TSW first space switches SSW, the respective signals are coupled to the appropriate or desired output port TSW, which are then Scent time slots in the correct order to be sent out on any crossover is accomplished through the AU-4 signal.

5 In the following, the basic idea of the TS'S'TS'ST algorithm and its application in practice are explained in more detail in Tables 1-8 in the light of the example. In this case, in the example case, the notations are explained in connection with Figure 2, but now there are three switch blocks (TSW-SSW) on the input side, which for simplicity have only three input ports, and thus there are a total of 9 input ports. Rows 1-8 correspond to ports, and columns to time slots. The additional switch blocks in the middle block (cf. blocks 9 to 16 in Figure 1) are not shown in the tables to keep the presentation simpler.

Table 1 shows, in a simplified manner, the signals entering the switching network. According to the explanation of Figure 2, the signal (6,1) of the gate one in the time slot one should be connected to the output port 6 of the TS'S'TS'S'T switch 15 and in the time slot one. It will be seen that the incoming signals contain several cases where the signal has to be copied to several output ports. For example, in port four, one incoming signal (fourth row, first column: 8.2 / 3.1 / 1.2) must be copied to outputs 8.2, 3.1 and 1.2.

The arrangement of the signals of the TS'S'TS'S'T switching arrangement in the input blocks forms the most difficult part of the algorithm according to the invention. This example aims to give a more accurate picture of the implementation of the algorithm in the input blocks and more generally in other blocks as well.

The idea of the algorithm implementing the method according to the invention is to move the signals in the table below vertically, i.e. in the same time slot between the port-25 path and / or the blocks, so that no part of the switch block receives more signals than time slots. The number of signals in a given row of a given input group must likewise be equal to or less than the number of time slots. Vertical transfers can be continued to improve the situation until the conditions are met. As a general guide to the algorithm, one can look at the situation in loh-30 degrees and find out which signals to transmit are most useful. For example, a broadcast signal, i.e., a signal arrangement that is copied to multiple output ports first, may provide the most benefit. After this, there are fewer signals to be transmitted to achieve a solution to the problem.

Let's start from the example situation in Table 1 with the signals coming to the switching network 35.

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Table 1 6.1 __6 ^ 2__6 ^ 3__6j4__6 ^ __ 64 $ _ 4.1 __U__20__50__80_ 4.2 / 2.2 7.1 7.2 7.3 7.4 7.5 7.6 8.2 / 3.1 / 1.2 9, 1 / 4.3 8.3 1.3 ____ 10__1.5 / 3.2__ 8.4 3.3 / 8.5 | 2.3 1.6 5.2 4.4 / 5.3 9.2 2.4 / 9.3 2.5 9.4 4.5__915__50__Z6__8 ^ 6__9 ^ _ 3.4 / 5.5 5.6 | 3.5 3.6 / 4.6

Table 1 signal is provided to a first input side of the blocks in which the signals are designed to hold as far as possible so that a single vertical row is not the same degree of the two signal output port. When the input side of the TS-dragon-con problem has been solved, the output of each signal is solved. The routes can then be searched separately within each TS block. The problem to be solved is simple. In time switches, the signals must be arranged so that there is at most one signal in the column going to the same output port.

Table 2 shows the arrangement of the signals after the first time switch.

In the mode switch, the signals can then be connected to the desired port. In this case, selections are only made on the mode switch. Let us first consider the arrangement of signals in the state switches in the light of an example.

• · · • ·

Table 2 6.1 __6 ^ 2__6 ^ 3__6 ^ 4__6 ^ 5__6 ^ 6_ 2.1 __U__40__50__80__4.2 / 2.2 .0: 7.1 7.2 7.3 7.4 7.5 7.6 ~ • · «8.2 / 3.1 / 1.2 9.1 / 4.3 (*) I 1.3 8.3 ____ IA__1.5 / 3.2__ 3.3 / 8.5 1 8.4 2.3 1.6 5.2 2.5 2.4 / 9.3 9.2 4.4 / 5.3 9.4 4.5 __9 ^ 5__5A__2 ^ 6__9 ^ 6__816_ 5.6 3.5 3.6 / 4.6 3.4 / 5 5,997,600

Signals arrangement is now continued in the first space switch input side in the same way as the time switch, ie so that a single vertical row is not the same degree of the two gate signals. Here, for each vertical row, a situation is solved in such a way that no more than one signal going to the same end block enters a certain middle block. If this is not completely successful, the unresolved signals are transferred to extra blocks.

It will be seen that the signal (*) in row 4, column 2, cannot be processed by the active basic blocks of the middle stage according to the required conditions, whereby it is directed to the additional blocks, i.e. to the duplicate part of the middle blocks; thus, this signal does not appear in the following Tables 3-5. Table 3 shows the situation after the first mode switch from which the fan-out to the middle stage takes place.

Table 3 6.1 6.2 6.3 6.4 16.5 16.6 2.1 __y_jy_JM__8J__4.2 / 2.2 7.1 7.2 [4.1 7.4 17.5 7.6 8.2 / 3.1 / 1.2 1 1.4 1 1.6 ___ U3__83__1.5 / 3.2__ 3.3 / 8.5 (*) 1 8.4 2.3 9.5 12.4 / 9.3 9.2 19 .6 19.4 4.5__5I6__5A__226 ___ 8J> _ 5.2 l2.5 [3.5 13.6 / 4.6 U, 4 / 5.3 [3.4 / 5.5

It can be seen from Table 3, row 6, column 2, that this signal (*) must also be derived into additional middle blocks, because the following conditions cannot be met through the basic blocks: '· 15; therefore, this signal does not appear in the following Tables 4-8.

Based on Figure 1, we see that the outputs of the status switches are connected in each case so that the top output of the block (line 1, line 4, line 7) is connected to the first middle stage block, the second highest output (line 2, line 5, line 8) to the second middle stage block. , etc. Each middle stage block receives the outputs of the previous state-20 switch so that the top row (input ports 1, 4, 7) receives the top output of the previous block, the second row (input ports 2, 5, 8) the second output of the previous block, etc. in this way the situation at the input ports of the middle blocks is made according to Table 4, i.e. the situation after decentralization (after fan-out).

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Table 4 6.1 I 6.2 I 6.3 16.4 16.5 I 6.6 8.2 / 3.1 / 1.2 ____ M___L6_ 19.5 12.4 / 9.3 19.2 9.6 [9 .4 2.1 1 1.1 17.3 15.1 I 8.1 4.2 / 2.2 ___ y__y__1.5 / 3.2__ 4.5 5.6 5.4 12.6 8.6 7.1 17.2 14.1 17.4 17.5 7.6 ___ M__1Ά__ 5.2 12.5 3.5 [3.6 / 4.6 4.4 / 5.3 3.4 / 5.5

Using Table 4, consider the connections that must be made in the first state stage of the center block. The signal 6/1 (row 1, column 1) is moved downward by the line, since it is going to switch the output side of the most distal to the middle section (of which the output ports 4 to 6). The signal 8.2 / 3.1 / 1.2 (row 2, column 1) is first divided by 5: first the signal is copied down by 8.2 rows on the same basis as the signal 6/1 above (the output port of the signal 8.2 is in the third output block -you). The signal is also copied up one line, i.e. 3.1 / 1.2 is desired from the output ports located in the first output block (output ports 1-3). The same principle is continued for other signals. The initial situation of the 10 state connections made here is not shown separately.

In the next time switch stage, no connections are made in this example.

Central blocks the output side of the space switches are still switching mode, so that Table 5 shows the situation after the middle of blocks.

* · • · li

Table 5 li 97600 3.1 / 1.2 12.4 I 1.4 I 1.6 6.1 __6J2__613__6A__6.5__6.6 8.2 9.5 9.3 9.2 9.6 9.4 2.1 I 1.1 I 1.3 1 2.6 1.5 / 3.2 2.2 4.5 __5J3_JA_JU ___ 4.2_ [7.3 8.3 8.1 18.6 2.5 3.5 3.6 2.3 3.4 ~ 5.2 ___4J__4J > __ 4.4 / 5.3 5.5_ 7.1 17.2 I 8.4 17.4 7.5 7.6

Mid-spread signals from the blocks (fan-out) in a fixed manner the output side of the peripheral switches, in the same way as described in Table 3, the processing of the signals.

Table 6 shows the situation prior to the last two output-side degrees. It must now be remembered that in Tables 2 and 3 the signals marked with (*) were removed to the additional blocks. They were discussed there as well as for the active blocks explained above. Thus, the signals marked with an arrow (->) can also be processed, and they still need time connections, as they are located in the wrong time slots at this stage.

Table 6 _-> 3.3 ____ 3.1 / 1.2 2.4 I 1.4 1 1.6 2.1 __U__l_A__2 ^ 6__1.5 / 3.2 2.2_ 2.5 3.5 3.6 2.3 3.4 • · • · / _-> 4.3 ____ 6.1 6.2 6.3 6.4 6.5 6.6 4.5 __5 ^ 6__5.4_JM ___ 4j2_ 5.2 4.1 4.6 14.4 / 5, 3 5.5 ~ -> 9.1 -> 8.5 ____ 8.2 9.5 9.3 9.2 9.6 9.4 __. 7.3 ____ y__8.6 7.1 [7.2 8.4 [7.4 17.5 7.6 ~ 12 97600

Table 7 shows the situation after the last mode switches.

Table 7 1.2 1.1 1.3 1.4 1.5 1.6 2.1__20__20__20__20__20_ 3.1 1 3.3 3.5 1 3.6 3.2 3.4 4.5 1 4.3 I 4 , 1 4.6 4.4 4.2 5.2 __50__50__50__50__50_ 6,1__60__60__60__60__60_ 7.1 7.2 7.3 7.4 7.5 7.6 8.2 __80__M__§0__80__80_ 9.1 9.5 9.3 9.2 9.6 9 , 4

Finally, Table 8 shows the situation after the last time switches, i.e. the output signals of the whole switching network in this selected example case.

Table 8 1.1 1.2 1.3 1.4 1.5 1.6 2.1 __2.2__20__20__20__20_ 3.1 3.2 3.3 3.4 3.5 3.6 4.1 4.2 4.3 4.4 4, 5 4.6 5.1 __50__50__50__50__50_ 6.1 6.2 6.3 6.4 6.5 6.6 7.1 7.2 7.3 7.4 7.5 7.6 8.1 __80__80__M__80__80_ 9.1 9.2 9.3 9.4 9.5 9.6 In this context, it should also be noted that the example given in Tables 1 to 8 \. has been greatly reduced to maintain the clarity of the presentation. In practice, for example in the case of the switching network of Figure 1 with 128 inputs and outputs and 63 time slots, the signal connections should be illustrated by tables with 128 rows and 63 columns, i.e. 8064 signal cells, respectively. In addition, the representation representation corresponding to the actual situation expands significantly if, in addition, it is desired to present the connection situations of the "additional" blocks of the middle stages by means of corresponding tables.

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Although the above example considered a situation where the number of input and output ports in the middle stage is twice the number of ports in the input and output stages, it is known that a blockless network can be provided in the general case of m TS blocks in the input stage, 2n-1 STS in the middle stage. blocks and ST-5 blocks in the output stage if no copies are made.

It should also be noted that the presented method and cross-connect architecture do not limit the implementation to the model presented in the example, but averaging can be used at all SDH levels. In addition, the switching can be used for cross-linking both STM and other similar signals. Although the modular structure of the example is currently preferred, it does not, of course, limit the use of the invention to smaller, and especially larger, modules.

This application does not go into detail about an algorithm that implements the method, which can be implemented by many methods known to a person skilled in the art. The algorithm can advantageously be applied in a computer controller of a cross-connect device, wherein the inventive algorithm is characterized by what is stated in the claims.

• · * «·» · · · »• ·

Claims (6)

14 97600 A method for switching SDH STM-N signals in a TS ^ TS ^ T switching network, wherein the capacity of the middle stage (SSW-TSW-SSW) is greater than the capacity of the input or output stages, wherein the capacitances of the input or output stages of the middle stage are central sections are said active blocks and other blocks as auxiliary blocks, characterized in that a) a solution of signals that pass through the input side of the time and space switches, contacts (TSW-SSW, shown in Figure 1 on the left side) so al) that the time switches (TSW) outputs there are no more than one signal going to the same output port of the switching network in the same time slot; and a2) that at the outputs of the state switches (SSW), one or more signals to the same output block (SSW to TSW) do not go to the same middle block of the active middle stage; a3) whereby in the time switches and space switches Al and A2 stages of rat deprived of the desired 15-ruling signals are passed through the center stage more blocks of the output side of the space-time switches; b) providing a solution for signals passing through the middle stage STS switch blocks (SSW-TSW-SSW); and c) forming the solution to the signals that pass through the output side space and aikakyt-20 wipers (SSW-TSW, on the right side in Figure 1) therethrough. January 2 The method according to claim, characterized in that the input side of the al-ka-state switches (TSW-SSW) connecting to the signals of repeating steps al and a2 before the step a3 execution, wherein the steps of al and a2 of the center stage when playing the same center block into and out of the same output-side space the number of signals going to the time switch block 25 must not exceed the number of time slots. «« · January 3 or 2, the method according to claim, characterized in that the stages • · · · * * * al and a2 are set to a restriction that the same input-side space-time block Sender exchanged between the number of signals does not exceed the AU-4 signal capacity. • · · • «. Method according to one of the preceding claims, characterized in that. The method 30 first processes the AU-4 signals at the input stage ports, * .. * which are routed through the switch stages so that they are in each case primarily routed to the space-time-space block of the same middle stage (SSW-TSW-SSW 1, 2, ... 16 ). Method according to one of the preceding claims, characterized in that the connections of the broadcast signals are made in middle-stage space-time-space blocks 35 (SSW-TSW-SSW), the switching rule being that the broadcast signals are output to the space-time-space blocks (SSW-TSW-SSW) at the same time, i.e. in the corresponding time slots. Method according to one of the preceding claims, characterized in that in the middle stage (SSW-TSW-SSW) the signals are arranged only by means of the state switches 5 (SSW).