FI95520C - Method of adaptively locking a signal phase into a reference signal phase and an adaptive phase lock to a frequency signal frequency - Google Patents

Description

1 95520

The present invention relates to a method for adaptively locking a signal phase to a reference signal phase and a phase lock adaptive to the frequency of the reference signal.

10 In a phase lock, the phase comparator compares the phase of the clock signal obtained from or by dividing its own oscillator with the phase of the reference signal coming from it or by dividing the signal generated therefrom. The phase lock tends to keep the phase difference of the signals to be compared constant by controlling the frequency of the oscillator appropriately.

Only one predetermined frequency, or a limited number of multiples of this frequency, can be connected to known devices with a phase lock, so the phase lock normally requires that the frequency of the incoming reference signal be known to be constant. This is a disadvantage e.g. in current telephony, where exchanges have to be synchronized to external frequency standards of varying frequency. In general, the frequency of a frequency standard is some integer multiple (2.3..N) of a certain low base frequency Fn (e.g., 4 kHz).

The object of the present invention is to provide a phase lock adaptable to the frequency of an incoming reference signal, which is characterized by the following steps: - measuring the frequency of the incoming reference signal; 30 - based on the measurement result, the reference signal is converted by dividing it into a signal such that its frequency is the frequency of a phase-locked clock signal or a signal proportional thereto multiplied or divided by an integer, and 35 - a signal to lock the phase.

Thus, in the arrangement according to the invention, the nominal frequency of the incoming signal does not have to be known, but can be some multiple of the low fundamental frequency Fn. The basic frequency of the frequency standard, i.e. the frequency increment Fn and the maximum factor N, can of course be set for each application.

The invention also relates to a phase lock adaptable to the frequency of the reference signal. The invention can be applied to both analog and digital phase locks.

The various embodiments of the invention are characterized by what is stated in the claims below.

The invention will now be described in more detail by way of example with reference to the accompanying drawing, which shows a digital phase lock according to the invention, in this example in block diagram form.

The adaptive phase lock according to the invention shown in the figure is part of, for example, a synchronization unit of a telephone exchange, in which the exchange is synchronized to an external frequency standard, for example multiples of 4 kHz (N = 2.3 ... 4096). The phase lock according to the invention includes e.g. digital »· · 25 phase comparator and frequency meter 2, which calculates how many pulses of the high-frequency clock signal input to input R can fit between two consecutive (rise) edges input to the inputs x and y of the phase-comparable signals. The phase comparator and the frequency meter in this example 30 are one and the same device, thus denoted by the same reference numeral 2, but they may equally well be different devices within the scope of the invention.

The microcomputer 3 controlling the phase lock via its bus 8 periodically reads the results of the phase difference calculation and calculates a new control word for the phase lock oscillator • · 3 95520 5 on the basis thereof. The control word is converted by the D / A converter 4 into the control voltage of the oscillator.

The phase lock also includes programmable divisors 1 and 6 with division values N resp. M are microcomputer 5 configurable. The divider 1 generates a reference signal Fdin from the reference signal Fin coming to the phase lock to the phase comparator. The divider 6 generates a phase comparison signal Fd from the clock signal Fout of the oscillator.

In the initial situation, the microcomputer performs the determination of the nominal frequency of the incoming 10 signals Fin. For this purpose, 2/1 selectors 7a and 7b are added to the inputs R and x of the phase comparator / frequency meter 2, which are controlled by the microcomputer with the signal SEL. In the frequency measurement phase, the selectors are in position B. In this case, the phase comparator / frequency meter 15 calculates how many pulses of the incoming reference signal can fit between two consecutive (rise) edges of the signal Fd from the divider 6. The microcomputer 3 programs the divider 6 to program the frequency of the reference signal Fd to be sufficiently small according to the length of the measurement period and the required measurement accuracy 20. The required measurement accuracy depends on how close the allowable frequencies of the reference signal Fin can be. The frequency difference between the phase lock oscillator 5 and the incoming reference signal determines the nominal frequency value of the highest allowed Fin signal with a given base frequency value. For example, if the base frequency of the reference signal is 10 Hz, the reference signal Fin is a multiple of 10 Hz of 20.30..Nx10 Hz as described above. If, now due to the dimensional accuracy, the relative frequency difference must be at least 2 10 6, the list frequency of the reference signal Fin nim-30 may not exceed 5 MHz, otherwise the relative frequency difference · 1 · is below the above-mentioned minimum value.

The result of the phase comparator / frequency meter 2 at this stage indicates the nominal frequency of the reference signal coming to the microcomputer 3. The microcomputer 3 sets a value corresponding to 35 measured nominal frequencies for the programmable • · 1 4 95520 divider 1 and a constant value for the programmable divider 6. The divider chains are set so that they receive nominally equal frequency signals Fdin and Fd.

After setting the dividers, the microcomputer controls the selector 1 and 2 with the signal SEL to position A. Then the phase comparator / frequency meter 2 acts as a phase comparator and calculates how many pulses of the signal Fout 6 to the edge of the signal Fd (rise). The high frequency signal Fout of the crystal oscillator 5 is 16.384 MHz in one embodiment of the invention. The microcomputer 3 then tends to control the oscillator 5 so that the measurement value 15 obtained from the phase comparator, i.e. the phase difference between the signals Fdin and Fd, remains constant.

When you change the frequency standard, the microcomputer performs a new frequency determination. Thus, the same phase lock can also be used in different environments without <20 technical changes.

It will be apparent to those skilled in the art that the various embodiments of the invention are not limited to the above example, but may vary within the scope of the claims below.

• · 1 l

Claims (7)

A method for adaptively reading a clock signal (F00T) phase in the phases of different reference signals (FIN), characterized in that - the phase of an incoming reference signal is measured; - the reference signal (FIN) is converted ρέ basis of the measurement result by division into a signal (FDIN) such that its frequency corresponds to the frequency of the clock signal (F0UT) to be read or multiplied or divided by an integer against this proportional signal (FD) and that - the signal (FDIN) and the clock signal (FOUT) to be read or said signal (FD) are used as a phase comparator (2) reference signals for a reading of the clock signal phase, known per se. Method according to claim 1, characterized in that a phase comparison signal (FD) is formed by the signal (FOUT) to be read with a divisor (6), by means of which the frequency of the signal (FD) is adapted to the length of the measurement period and / or the required measurement accuracy. Method according to claim 1 or 2, characterized in that the frequency of the incoming reference signal (Fine) is determined by counting the number of reference signal pulses within a time interval between two pulses in the phase comparison signal (FD) generated from the signal (FUT). ) to be phased. A phase reading circuit adapted to the frequency of a reference signal, the phase reading circuit comprising a phase comparator for comparing the signal to be read phase with the reference signal, characterized in that the phase reading circuit comprises a frequency meter (2) for determining an incoming reference signal (FIN). frequency, a programmable device for division (1) for converting the incoming reference signal (FIN) into a signal - · · 8 95520 (FDin) used as a first reference signal in a phase comparator (2) whose frequency corresponds to the frequency of the clock signal (FUT) to be read or one multiplied or divided by the integer signal (FD) by an integer, and means (6) for using the clock signal (F00T) to be phased or said signal (FD) as a second reference signal in the phase comparator (2). 5. The phase reading circuit according to claim 4, characterized in that the phase reading circuit comprises a device for division (6), which device generates the signal (F0UT) to be read a phase comparison signal (FD), which device can be programmed to adapt the signal. frequency (FD) frequency to the length of the measurement period and / or the required measurement accuracy. 15 6. A phase reading circuit according to claim 4 or 5, characterized in that it comprises the coupling means (7a, 7b), which, when the phase reading circuit is in its measuring frequency (FIN), is set to control the reference signal of the phase comparator (2). A purity signal (FIN), the frequency of which can be defined by comparison with the phase comparison signal (FD), and, where the phase reading circuit is in the phase reading state, the switching means (7a, 7b) are set to control the phase comparator (2) signal (Fqot) / which can be phased into a reference signal and as between two pulse edges of the signals (FD111, FD) during phase comparison, a number of pulses contain, on the basis of which the number of phase difference between the signals can be determined. · II