WO1994015400A1 - A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal - Google Patents

A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal Download PDF

Info

Publication number
WO1994015400A1
WO1994015400A1 PCT/FI1993/000558 FI9300558W WO9415400A1 WO 1994015400 A1 WO1994015400 A1 WO 1994015400A1 FI 9300558 W FI9300558 W FI 9300558W WO 9415400 A1 WO9415400 A1 WO 9415400A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
signal
frequency
reference signal
ouτ
Prior art date
Application number
PCT/FI1993/000558
Other languages
French (fr)
Inventor
Markku Ruuskanen
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to AU57008/94A priority Critical patent/AU5700894A/en
Publication of WO1994015400A1 publication Critical patent/WO1994015400A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • This invention relates to a method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal.
  • a phase comparator compares the phase of a clock signal obtained from an associ ⁇ ated oscillator or a clock signal obtained by divid ⁇ ing that signal with the phase of an input reference signal or a signal obtained by dividing that signal.
  • the phase lock tries to keep a constant phase difference between the signals to be compared.
  • the frequency of a frequency standard usually is some integer multiple (2, 3..N) of a given low basic frequency Fn (e.g. 4 kHz).
  • the object of this invention is to provide a phase lock adaptive to the frequency of an input ref- erence signal, which phase lock is characterized by the following steps:
  • the frequency of the input reference signal is determined by measuring and the determined refer ⁇ ence signal F IN is converted by dividing to a signal FD 1N , the frequency of which is some integer multiple of the frequency of a clock signal F ou ⁇ to be phase locked or the frequency of the clock signal to be phase locked divided by some integer, and
  • the nominal frequency of the input signal does not need to be known, but it may be any multiple of the low basic frequency Fn.
  • the basic frequency of the frequency standard, i.e. the fre ⁇ quency increment Fn, and the maximum factor N may naturally be set as per application.
  • a further object of the invention is a phase lock adaptive to the frequency of the reference sig ⁇ nal.
  • the invention may be applied both to analog and digital phase locks.
  • the separate embodiments of the invention are characterized in what is set forth in the appended claims.
  • the phase lock accord ⁇ ing to the invention includes a digital phase compa- rator and a frequency meter 2, which counts how many pulses of a high-frequency clock signal applied to an input R go between two successive (rising) edges ap ⁇ plied to inputs x and y of signals to be phase com ⁇ pared.
  • the phase comparator and the frequency meter are one single device, thus indicated by the same reference numeral 2, but they may just as well be separate devices within the scope of the in ⁇ vention.
  • a microcomputer 3 controlling the phase lock over its bus 8 reads at fixed intervals the results of counting the phase difference, and calculates a new control word for an oscillator 5 to be phase locked on the basis of these results.
  • the control word is converted to a control voltage of the oscil- lator by means of a D/A converter 4.
  • the phase lock further comprises programmable dividers 1 and 6 with division values N and M, re ⁇ spectively, which values may be set by the microcom ⁇ puter.
  • the divider 1 generates from an input refer- ence signal F IN of the phase lock a reference signal FD IN for the phase comparator.
  • the divider 6 generates a phase comparison signal F D from a clock signal F ou ⁇ of the oscillator.
  • the microcomputer performs a determination of the nominal frequency of the input signal F IN .
  • 2/1 selectors 7a and 7b are added to the inputs R and x of the phase comparator/frequency meter 2, which selectors are controlled by the microcomputer by means of a signal SEL.
  • the selectors are in a position B.
  • the phase com ⁇ parator/frequency meter counts how many pulses of the input reference signal go between two successive (rising) edges of the signal F D obtained from the di- vider 6.
  • the microcomputer 3 programs the frequency of the reference signal F D low enough as per the length of the measuring period and the required accuracy of measurement.
  • the re ⁇ quired accuracy of measurement depends on how close to each other the allowable frequencies of the refer ⁇ ence signal F IN may be.
  • the frequency difference be ⁇ tween the oscillator 5 and the input reference signal of the phase lock determines the highest permitted value of the nominal frequency of the signal F IN with a given basic frequency value. For instance, if the basic frequency of the reference signal is 10 Hz, the reference signal F IN is according to the above a mul ⁇ tiple of 10 Hz, 20, 30..NxlO Hz. If the relative fre ⁇ quency difference now shall be at least 2xl0 "6 , be- cause of the accuracy of measurement, the nominal frequency of the reference signal F 1N may be 5 MHz at the most, otherwise the relative frequency difference is lower than said minimum value.
  • the result of the phase comparator/frequency meter 2 detects at this stage the nominal frequency of the input ref rence signal to the microcomputer 3.
  • the microcomputer 3 sets a value corresponding to the measured nominal frequency for the programmable di ⁇ vider 1 and a constant value for the programmable di- vider 6.
  • the divider chains are set in such a manner that the signals FD IN and F D obtained therefrom have nominally the same frequency.
  • the microcom ⁇ puter controls the selectors 1 and 2 to a position A by means of the signal SEL.
  • the phase compa ⁇ rator/frequency meter 2 acts as a phase comparator, and counts how many pulses of the signal F ou ⁇ generated by the oscillator 5 to be phase locked go between the (rising) edge of the reference signal FD IN obtained from the divider 1 and the (rising) edge of the sig- nal F D generated by the divider 6 from the oscillator signal.
  • the high-frequency signal F ou ⁇ of the crystal oscillator 5 is 16,384 MHz in one embodiment of the invention.
  • the microcomputer When the frequency standard is changed, the microcomputer performs a new frequency determination.
  • the same phase lock may also be used in differ ⁇ ent environments without technical changes.

Abstract

The invention relates to a method of locking a clock signal (FOUT) phase adaptively to the phase of different reference signals (FIN) and to a phase lock implementing the method. According to the invention, the frequency of an input reference signal is determined by measuring and the determined reference signal (FIN) is converted by dividing to a signal (FDIN), the frequency of which is some integer multiple of the frequency of the clock signal (FOUT) to be phase locked, or the frequency of the clock signal to be phase locked divided by some integer. The signal (FDIN) and the clock singal (FOUT) to be phase locked or a signal (FD) proportional thereto are used as reference signals of a phase comparator (2) for locking the clock signal phase in a manner known per se.

Description

A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal
This invention relates to a method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal.
In a phase lock, a phase comparator compares the phase of a clock signal obtained from an associ¬ ated oscillator or a clock signal obtained by divid¬ ing that signal with the phase of an input reference signal or a signal obtained by dividing that signal. By means of a suitable control of the oscillator fre- quency, the phase lock tries to keep a constant phase difference between the signals to be compared.
Only one predetermined frequency or a limited number of multiples of this frequency may be switched to known devices containing a phase lock, and there- fore, the phase lock usually requires that the fre¬ quency of the input reference signal is a known con¬ stant. This is a drawback in present telephone tech¬ nique, for instance, in which exchanges have to be synchronized with external frequency standards with variable frequencies. The frequency of a frequency standard usually is some integer multiple (2, 3..N) of a given low basic frequency Fn (e.g. 4 kHz).
The object of this invention is to provide a phase lock adaptive to the frequency of an input ref- erence signal, which phase lock is characterized by the following steps:
- the frequency of the input reference signal is determined by measuring and the determined refer¬ ence signal FIN is converted by dividing to a signal FD1N, the frequency of which is some integer multiple of the frequency of a clock signal Fouτ to be phase locked or the frequency of the clock signal to be phase locked divided by some integer, and
- the signal FDIN and the clock signal Fouτ to be phase locked or a signal FD proportional thereto are used as reference signals of a phase comparator for locking the clock signal phase in a manner known per se.
Consequently, in the arrangement according to the invention, the nominal frequency of the input signal does not need to be known, but it may be any multiple of the low basic frequency Fn. The basic frequency of the frequency standard, i.e. the fre¬ quency increment Fn, and the maximum factor N may naturally be set as per application.
A further object of the invention is a phase lock adaptive to the frequency of the reference sig¬ nal. The invention may be applied both to analog and digital phase locks. The separate embodiments of the invention are characterized in what is set forth in the appended claims.
In the following, the invention will be de¬ scribed in greater detail by means of an example re- ferring to the attached drawing, which shows a block diagram of a phase lock according to the invention, in this example a digital phase lock.
The figure shows an adaptive phase lock accord¬ ing to the invention, constituting a part of a syn- chronizing unit of a telephone exchange, for in¬ stance, in which unit the exchange is synchronized with an external frequency standard, e.g. with multi¬ ples of 4 kHz (N=2, 3...4096). The phase lock accord¬ ing to the invention includes a digital phase compa- rator and a frequency meter 2, which counts how many pulses of a high-frequency clock signal applied to an input R go between two successive (rising) edges ap¬ plied to inputs x and y of signals to be phase com¬ pared. In this example, the phase comparator and the frequency meter are one single device, thus indicated by the same reference numeral 2, but they may just as well be separate devices within the scope of the in¬ vention.
A microcomputer 3 controlling the phase lock over its bus 8 reads at fixed intervals the results of counting the phase difference, and calculates a new control word for an oscillator 5 to be phase locked on the basis of these results. The control word is converted to a control voltage of the oscil- lator by means of a D/A converter 4.
The phase lock further comprises programmable dividers 1 and 6 with division values N and M, re¬ spectively, which values may be set by the microcom¬ puter. The divider 1 generates from an input refer- ence signal FIN of the phase lock a reference signal FDIN for the phase comparator. The divider 6 generates a phase comparison signal FD from a clock signal Fouτ of the oscillator.
In the initial situation, the microcomputer performs a determination of the nominal frequency of the input signal FIN. For this purpose, 2/1 selectors 7a and 7b are added to the inputs R and x of the phase comparator/frequency meter 2, which selectors are controlled by the microcomputer by means of a signal SEL. At the measurement of the frequency, the selectors are in a position B. Hereby the phase com¬ parator/frequency meter counts how many pulses of the input reference signal go between two successive (rising) edges of the signal FD obtained from the di- vider 6. By means of the divider 6, the microcomputer 3 programs the frequency of the reference signal FD low enough as per the length of the measuring period and the required accuracy of measurement. The re¬ quired accuracy of measurement depends on how close to each other the allowable frequencies of the refer¬ ence signal FIN may be. The frequency difference be¬ tween the oscillator 5 and the input reference signal of the phase lock determines the highest permitted value of the nominal frequency of the signal FIN with a given basic frequency value. For instance, if the basic frequency of the reference signal is 10 Hz, the reference signal FIN is according to the above a mul¬ tiple of 10 Hz, 20, 30..NxlO Hz. If the relative fre¬ quency difference now shall be at least 2xl0"6, be- cause of the accuracy of measurement, the nominal frequency of the reference signal F1N may be 5 MHz at the most, otherwise the relative frequency difference is lower than said minimum value.
The result of the phase comparator/frequency meter 2 detects at this stage the nominal frequency of the input ref rence signal to the microcomputer 3. The microcomputer 3 sets a value corresponding to the measured nominal frequency for the programmable di¬ vider 1 and a constant value for the programmable di- vider 6. The divider chains are set in such a manner that the signals FDIN and FD obtained therefrom have nominally the same frequency.
After the dividers have been set, the microcom¬ puter controls the selectors 1 and 2 to a position A by means of the signal SEL. Thereby the phase compa¬ rator/frequency meter 2 acts as a phase comparator, and counts how many pulses of the signal Fouτ generated by the oscillator 5 to be phase locked go between the (rising) edge of the reference signal FDIN obtained from the divider 1 and the (rising) edge of the sig- nal FD generated by the divider 6 from the oscillator signal. The high-frequency signal Fouτ of the crystal oscillator 5 is 16,384 MHz in one embodiment of the invention. After this, the microcomputer 3 tries to control the oscillator 5 so that the measuring value to be obtained from the phase comparator, i.e. the phase difference between the signals FDIN and FD, would remain constant.
When the frequency standard is changed, the microcomputer performs a new frequency determination. Thus the same phase lock may also be used in differ¬ ent environments without technical changes.
It is clear for one skilled in the art that the various embodiments of the invention are not limited to the example presented above, but that they may vary within the scope of the claims set forth below.

Claims

Claims:
1. A method of locking a clock signal (Fouτ) phase adaptively to the phase of different reference signals (FIN), c h a r a c t e r i z e d in that
- the frequency of an input reference signal is determined by measuring and the determined reference signal (FIN) is converted by dividing to a signal (FDIN), the frequency of which is some integer multi- pie of the frequency of the clock signal (Fouτ) to be phase locked or the frequency of the clock signal to be phase locked divided by some integer, and that
- the signal (FD1N) and the clock signal (Fouτ) to be phase locked or a signal (FD) proportional thereto are used as reference signals of a phase com¬ parator (2) for locking the clock signal phase in a manner known per se.
2. A method according to claim 1, c h a r a c¬ t e r i z e d in that a phase comparison signal (FD) is generated from the signal (Fouτ) to be phase locked by means of a divider (6), by which the frequency of the signal (FD) is made appropriate considering the length of a measuring period and/or the accuracy of measuring required.
3. A method according to claim 1 or 2, c h a r a c t e r i z e d in that the frequency of the input reference signal (FIN) is determined by counting the number of reference signal pulses within a time interval constituted by two pulses of the phase comparison signal (FD) generated from the signal (Fouτ) to be phase locked.
4. A phase lock adaptive to the frequency of a reference signal, which phase lock comprises a phase comparator for comparing a signal to be phase locked with the reference signal, c h a r a c t e r i z e d in that the phase lock comprises a frequency meter (2) for determining the frequency of the input refer¬ ence signal (FIN) , a programmable divider ( 1 ) for con¬ verting the input reference signal (FIN) to a signal (FD1N) to be used as a first reference signal in the phase comparator (2), the frequency of which is some integer multiple of the frequency of the clock signal (Fouτ) to be phase locked or the frequency of the clock signal to be phase locked divided by some integer, as well as means (6) for using the clock signal (Fouτ) to be phase locked or a signal (FD) proportional thereto as a second reference signal in the phase comparator (2).
5. A phase lock according to claim 4, c h a r- a c t e r i z e d in that the phase lock comprises a divider ( 6) generating the phase comparison signal (FD) from the signal (Fouτ) to be phase locked, which divider may be programmed to make the frequency of the signal (FD) appropriate considering the length of a measuring period and/or the accuracy of measuring required.
6. A phase lock according to claim 4 or 5, c h a r a c t e r i z e d in that it comprises switching means (7a, 7b), which, with the phase lock in a state of measuring the reference frequency (FIN), are set to control said reference signal (FIN) to be the reference signal of the phase comparator (2), the frequency of which reference signal may be determined by comparing it with the phase comparison signal (FD), and that the switching means (7a, 7b), with the phase lock in a phase locking state, are set to control said signal Fouτ to be phase locked to be the reference signal of the phase comparator (2) , whereby the phase difference between the phase comparison signals (FDIN-- F D) maY be determined on the basis of the number of pulses going between two pulse edges of these sig¬ nals.
PCT/FI1993/000558 1992-12-29 1993-12-28 A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal WO1994015400A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU57008/94A AU5700894A (en) 1992-12-29 1993-12-28 A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI925918 1992-12-29
FI925918A FI95520C (en) 1992-12-29 1992-12-29 Method of adaptively locking a signal phase into a reference signal phase and an adaptive phase lock to a frequency signal frequency

Publications (1)

Publication Number Publication Date
WO1994015400A1 true WO1994015400A1 (en) 1994-07-07

Family

ID=8536473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1993/000558 WO1994015400A1 (en) 1992-12-29 1993-12-28 A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal

Country Status (3)

Country Link
AU (1) AU5700894A (en)
FI (1) FI95520C (en)
WO (1) WO1994015400A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4107612A (en) * 1976-05-05 1978-08-15 Frederick Electronics Corporation Phase locked loop exciter generator for high frequency transmitter
FR2564664A1 (en) * 1984-05-15 1985-11-22 Adam Pierre Device for recovering a periodic signal
WO1989012931A1 (en) * 1988-06-13 1989-12-28 Unisys Corporation Fast locking phase-locked loop utilizing frequency estimation
EP0416840A2 (en) * 1989-09-08 1991-03-13 Delco Electronics Corporation Phase locked loop circuit with digital control
EP0500516A2 (en) * 1991-02-20 1992-08-26 Telefonaktiebolaget L M Ericsson Broad band frequency synthesizer for quick frequency retuning

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4107612A (en) * 1976-05-05 1978-08-15 Frederick Electronics Corporation Phase locked loop exciter generator for high frequency transmitter
FR2564664A1 (en) * 1984-05-15 1985-11-22 Adam Pierre Device for recovering a periodic signal
WO1989012931A1 (en) * 1988-06-13 1989-12-28 Unisys Corporation Fast locking phase-locked loop utilizing frequency estimation
EP0416840A2 (en) * 1989-09-08 1991-03-13 Delco Electronics Corporation Phase locked loop circuit with digital control
EP0500516A2 (en) * 1991-02-20 1992-08-26 Telefonaktiebolaget L M Ericsson Broad band frequency synthesizer for quick frequency retuning

Also Published As

Publication number Publication date
FI925918A0 (en) 1992-12-29
AU5700894A (en) 1994-07-19
FI95520B (en) 1995-10-31
FI95520C (en) 1996-02-12
FI925918A (en) 1994-06-30

Similar Documents

Publication Publication Date Title
US5920233A (en) Phase locked loop including a sampling circuit for reducing spurious side bands
US5182528A (en) Frequency synthesizer having microcomputer supplying analog and digital control signals to VCO
US3973209A (en) Digital arithmetic synthesizer phase lock loop with direct doppler and frequency readout
EP0218406A2 (en) Sampling clock generation circuit
US5828678A (en) Digital audio resolving apparatus and method
US4005479A (en) Phase locked circuits
US5349310A (en) Digitally controlled fractional frequency synthesizer
US4105948A (en) Frequency synthesizer with rapidly changeable frequency
US4864253A (en) Phase locked loop wherein phase comparing and filtering are performed by microprocessor
GB2026268A (en) Frequency synthesizers
US4105946A (en) Frequency synthesizer with phase locked loop and counter
US3883817A (en) Digital phase-locked loop
US4706040A (en) Frequency synthesizer circuit
EP0164785B1 (en) Electric circuit arrangement comprising a phase control-circuit
JPS6247379B2 (en)
US6757349B1 (en) PLL frequency synthesizer with lock detection circuit
US4225830A (en) Plural phase locked loop frequency synthesizer
US4145667A (en) Phase locked loop frequency synthesizer using digital modulo arithmetic
US5036297A (en) High-speed digital PLL device
US4257018A (en) Automatic tuning circuits for voltage controlled filters, by digital phase control
US4540945A (en) Variable-frequency oscillation circuit
JP2000502867A (en) Method and apparatus for frequency modulation of high frequency signal
WO1994015400A1 (en) A method of locking a signal phase adaptively to a reference signal phase and a phase lock adaptive to the frequency of the reference signal
GB2112236A (en) Digital device for clock signal synchronization
EP0076009B1 (en) Tuning circuit incorporating a frequency synthesizer circuit

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU DE GB RU SE US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642