FI87125C - Method for encoding a line signal - Google Patents

Description

! 87125

The present invention relates to a method for encoding a line signal for use in a digital communication system in which the clocks of all multiplexed hierarchies are synchronous, in which method the line signal is formed of multi-bit bytes.

Traditionally, a plesiochronous system has been used in Europe, in which each multiplexed hierarchy has its own defined clock rate and each typically 5B6B-encoded wire signal still has its own clock rate. Although the voice channel numbers in the hierarchies increase by 1: 4, the corresponding clock rates do not follow the same integer law. As a result, 15 devices have wholesale different phase locks and bit compensations, and access from individual hierarchy levels to individual sub-hierarchy channels has been quite complex.

SDH 20 (Synchronous Digital Hierarchy), which is currently being defined by CCITT, and its American ancestor SONET, bring a tremendous improvement, as in the new system all multiplexer stages and cross-connects operate clockwise. Thus, even slow signals are multiplexed into a 155 Mbit / s basic frame with a clock of 25 155 Mbit / s, but using only a part of its time slots. High transmission speeds, in turn, are integer multiples of the basic speed of 155 Mbit / s. There is no wire coding to increase the clock speed.

However, the uncoded SDH lead signal is a potential source of problems, as the system is not ultimately independent of the bit sequence of the signal. Long random unipolar bit strings on the line and bit strings with little clock information may cause transmission error bursts under poor conditions. It is an object of the present invention to provide a method for encoding a line signal which is able to achieve the same advantages over previously used systems as an SDH system, but which nevertheless succeeds in avoiding the problems mentioned above. This is achieved by the method according to the invention, which is characterized in that the bytes are formed by successively interleaving a predetermined number of useful signal bits or bytes and one or more additional bits for later use in encoding the line signal. In principle, such a method of generating a line signal is inefficient because, for example, it has eight data bits for each nine-bit period and one additional bit which does not transmit data. However, by utilizing this additional bit, the balance of the line signal can be substantially improved by the line portion 15 and its timing information can be increased.

A preferred and simple way of carrying out the invention is provided by a procedure in which the additional bit is a parity bit which ensures that at least one state change occurs in the line signal for each period.

According to another preferred method, the additional bit can be utilized such that the lead signal is encoded such that when the additional bit is at its second value, the states of said predetermined payload bit bit are not interfered with and the additional bit is at its second value.

Alternatively, it is also possible to determine the value of the 30 additional bits by monitoring the useful signal bits and assigning a value to the additional bit based on this monitoring, which improves the balance of the control signal and / or its clock content.

In the following, a method according to the invention for encoding a wiring signal will be described in more detail with reference to the accompanying drawing, in which Fig. 1 illustrates a structure of a digital communication system utilizing a coding method according to the invention; the structure of a digital communication system suitable for implementing the embodiment, and Fig. 4 illustrates the structure of a digital communication system suitable for implementing the second embodiment of the coding method according to the invention.

Figure 1 shows the basic structure of a digital communication system suitable for implementing the coding method according to the invention. The transmitter of the system consists of multiplexers 1 of different hierarchical levels and a line encoder 2, from which the line signal is output. All multiplexers 1 and line encoder 2 are timed at the same clock C. Thus, although this system utilizes the basic principle that a line signal consists of consecutive constant length bytes and all hierarchy levels have the same or integer clock frequency, the line signal is nevertheless coded. that the problems associated with the uncoded line signal can be avoided, at least for the most part. The coding is then based on the fact that the line signal is formed according to Fig. 2 by successively interleaving a predetermined number of signal or data bits or bytes and between them one or more additional bits for use in the coding. In the example of Figure 2, there are always eight consecutive data bits and there is always one additional bit between such eight-bit periods or bytes. The line encoder 2 shown in Figure 1 operates on the basis of these 35 additional bits.

87125 4

A 1 + 8 bit model such as that shown in Figure 2 is ideally suited for SDH-type signal processing, where all multiplexings, cross-connections, etc. take place in byte-based and parallel form. In multiplexing 5, the empty bits added in front of the eight-bit data signal bytes, i.e. octets, remain in exactly their own places through all intermediate processes and appear at regular intervals when entering the wire encoder after multiplexing, where they are utilized to encode the wire signal.

Figure 3 illustrates one simple system for performing this coding. In this example according to Fig. 3, the additional bit is used as a parity bit, which ensures that for each period, i.e. in the case of the signal according to Fig. 2, there is at least one state change in the line signal per group of nine bits. Such simple coding can be achieved only by means of the block 3 shown in Fig. 3, which gives the values of the additional bits of the line signal as mentioned above. However, in the system according to Fig. 3, a block 4 is arranged between the multi-plexers 1 and the block 3 giving the additional bit parity value, which is a frame-locked data modifier also applied in SDH and which breaks special queues which may come from empty ATM blocks, for example. signals or 25 channels that have not been activated. With this data modifier 4, only the useful bits of the line signal are messed up without affecting the additional bits at all. However, the balancing effect of the use of the parity bit on the line signal is relatively small, so when using such coding, the receivers have to be constructed in such a way that they can tolerate even quite strong imbalances in the line signal. In addition to somewhat improving the balance of the control signal, the parity bit above all ensures the adequacy of its clock content.

Figure 4 shows another way of applying the coding method according to the invention. In this method, the lead signal is encoded so that when the additional bit is at its second value, the octet or byte preceding this additional bit is not interfered with, and when the additional bit is at its second value, the bits of the octet preceding this additional bit are inverted. In this way, the wire signal can be coded so that the result is even a balanced wire signal. The system illustrated in Figure 4 is capable of providing such coding. It first comprises a precoder 5 which inverts every other bit as an example. Thus, it corresponds to a simple data editor. In this way, the monotonic special queues produced by relatively common unfurnished sub-hierarchies and AIS signals receive more timing information. After this precoding, the data 15 is routed to the byte register 6 and in parallel with it to the byte digital sum calculating unit 7. The coded wire signal from the byte register 6 is in turn also directed to the current digital sum calculating unit 8. These sums from blocks 7 and 8 are verified by a comparator 9 is able to monitor the balance of the control signal. When the imbalance is large, the comparator outputs control to byte register 6, which causes the byte bits to be inverted and at the same time gives the additional bit a value of 0, for example, knowing that the byte preceding this 25 bits is inverted. If there is no imbalance, the additional bit is given a value of 1, which is known not to be tampered with in the byte preceding the bit.

An alternative way of carrying out the method according to the invention is provided by a method in which the lead signal is monitored proactively and, on the basis of this monitoring, the polarities of the additional bits are reversed if necessary. Alternatively, either the balance of the control signal or its clock content, or possibly both, can be improved. Such predictive monitoring of the line signal 35 can be accomplished by using the data buffer and the auxiliary modification 87125 6 preceding it. It would even be conceivable that, prior to the actual data editing, a kind of pre-editing using two types of fill bit selection would be performed synchronously with this. For example, the method that produced the most state-5 switches could then be selected for the actual payload signal process after the buffer.

Some simple ways of carrying out the method according to the invention have been described above, in particular when it is desired that the apparatus implementing the method remain simple. Utilizing the interleaved line signal according to the invention could also provide more efficiently balanced encodings, but such encodings would require fast memories and a lot of peripheral logic. It is further conceivable that not all of the extra bits-15 would be used for encoding but that some of them would be reserved for other purposes. Thus, it is to be understood that the method alternatives described above may be varied without departing from the scope of the appended claims.

Claims (4)

A method for encoding a line signal to be used in a digital telecommunication system, wherein all clocks for the multiplexed hierarchies are synchronous, in which method the line signal is formed from multi-bit syllables, characterized in that the syllables are formed successively lameHere a predetermined number of utility signal bits or syllables and one or more extra bits to be used later for encoding the line signal. Method according to claim 1, characterized in that the extra bit is a parity bit, which ensures that for each period in the line signal 15 there is at least one change of state. Method according to claim 1, characterized in that the line signal is encoded such that where the extra bit is in its one value, the state of the bits of said predetermined useful signal number preceding this extra bit is not changed and the extra bit is in its second value, the bits are inverted by said predetermined utility signal bit number which precedes this extra bit. 4. A method as claimed in claim 1, characterized in that the value of the extra bit is determined by observing utility signal bits and by giving that extra bit a value which improves the balance of the line signal and / or its clockwise.