FI854910A0 - Anordning foer distortionsfri utstrykning av display under en enskild bild. - Google Patents

Anordning foer distortionsfri utstrykning av display under en enskild bild.

Info

Publication number
FI854910A0
FI854910A0 FI854910A FI854910A FI854910A0 FI 854910 A0 FI854910 A0 FI 854910A0 FI 854910 A FI854910 A FI 854910A FI 854910 A FI854910 A FI 854910A FI 854910 A0 FI854910 A0 FI 854910A0
Authority
FI
Finland
Prior art keywords
enskild
anordination
dispension
bild
distortions
Prior art date
Application number
FI854910A
Other languages
English (en)
Other versions
FI854910A (fi
Inventor
Kenneth E Bruce
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of FI854910A0 publication Critical patent/FI854910A0/fi
Publication of FI854910A publication Critical patent/FI854910A/fi

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
FI854910A 1984-12-14 1985-12-12 Anordning foer distortionsfri utstrykning av display under en enskild bild. FI854910A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/681,537 US4701863A (en) 1984-12-14 1984-12-14 Apparatus for distortion free clearing of a display during a single frame time

Publications (2)

Publication Number Publication Date
FI854910A0 true FI854910A0 (fi) 1985-12-12
FI854910A FI854910A (fi) 1986-06-15

Family

ID=24735690

Family Applications (1)

Application Number Title Priority Date Filing Date
FI854910A FI854910A (fi) 1984-12-14 1985-12-12 Anordning foer distortionsfri utstrykning av display under en enskild bild.

Country Status (4)

Country Link
US (1) US4701863A (fi)
EP (1) EP0186070A3 (fi)
AU (1) AU5089385A (fi)
FI (1) FI854910A (fi)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226119A (en) * 1985-07-03 1993-07-06 Hitachi, Ltd. Graphic display controller
GB2181929B (en) * 1985-10-21 1989-09-20 Sony Corp Methods of and apparatus for video signal processing
JPH07117886B2 (ja) * 1985-11-28 1995-12-18 キヤノン株式会社 デ−タ制御装置
US4809189A (en) * 1986-10-09 1989-02-28 Tektronix, Inc. Equivalent time waveform data display
JP2692081B2 (ja) * 1987-06-12 1997-12-17 ミノルタ株式会社 画像メモリのアドレス制御方式
US5025394A (en) * 1988-09-09 1991-06-18 New York Institute Of Technology Method and apparatus for generating animated images
WO1990002780A1 (en) * 1988-09-13 1990-03-22 Silicon Graphics, Inc. Method and apparatus for clearing a region of a z-buffer
US5038297A (en) * 1988-09-13 1991-08-06 Silicon Graphics, Inc. Method and apparatus for clearing a region of Z-buffer
US5008838A (en) * 1989-11-17 1991-04-16 Digital Corporation Method for simultaneous initialization of a double buffer and a frame buffer
JPH04140892A (ja) * 1990-02-05 1992-05-14 Internatl Business Mach Corp <Ibm> 制御データをエンコードする装置及び方法
US5233689A (en) * 1990-03-16 1993-08-03 Hewlett-Packard Company Methods and apparatus for maximizing column address coherency for serial and random port accesses to a dual port ram array

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559742B2 (fi) * 1974-06-20 1980-03-12
US4143360A (en) * 1976-08-27 1979-03-06 The Magnavox Company Method and apparatus for controlling a display terminal
US4270125A (en) * 1976-09-13 1981-05-26 Rca Corporation Display system
US4342029A (en) * 1979-01-31 1982-07-27 Grumman Aerospace Corporation Color graphics display terminal
US4232311A (en) * 1979-03-20 1980-11-04 Chyron Corporation Color display apparatus

Also Published As

Publication number Publication date
EP0186070A3 (en) 1988-10-05
US4701863A (en) 1987-10-20
EP0186070A2 (en) 1986-07-02
AU5089385A (en) 1986-06-19
FI854910A (fi) 1986-06-15

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Legal Events

Date Code Title Description
MM Patent lapsed

Owner name: HONEYWELL INFORMATION SYSTEMS INC.