FI74181C - Continuously expandable clutch field - Google Patents

Description

77Ϊ5Ξ7 | ANNOUNCEMENT _. . _ „PJ (11) UTLÄGGNINGSSKRIFT 74181 (51) Kv.lk.Vlnt CI4 Η ΟΑ Q 3/68

SUOMI FINLAND

(Π) (21) Patent application-Patentansökning 780370 (22) Application date - Ansökningsdag 06.02.78

National Board of Patents and Registration (23) Starting date-Giinghetsdag 06.02.78

Patent-och registerstyrelsen (41) Tuiiutjuik.seksi-Bi.vitofhmtng 08.08.78 (44) Date of presentation and publication - -? 1 08.87

Ansökan utlagd och utl skriften publicerad (86) International Application - Int ansökan (32) (33) (31) Claim Requested - Begärd Priority 07-02.77 US (US) 766396 (71) Alcatel NV, De Lairessestraat 153, Amsterdam, AIankomaat- Neder1änderna (NL) (72) Kenneth Frank Giesken, Fairfield, Connecticut,

John Michael Cotton, East Norwalk, Connecticut, USA (7b) Oy Kolster Ab (5b) Continuously expandable switch field -Kontinuer1igt expanderbart koppiingsfält The present invention relates to connections for space and time division transmission systems and in particular to a new switch element and switch field system for implements a substantially continuously expandable switch field in telephone exchanges, automatic subscriber exchanges (PABXs), remote hubs, data circuit breakers, and other devices requiring multiple intermediate connections.

Currently available switch fields use time slot switching modules or space switching modules that use split-mode space switching, usually with two time modules and one space module, or time modules one and two space modules. U.S. Patent No. 3,770,895 discloses prior art time slot switching. U.S. Patent No. 3,963,872 discloses a multi-stage rotary switch field according to the prior art. These prior art switch fields generally cannot be converted to large system size expansions without large re-cabling.

Prior art switch fields are designed for a specific size need, i.e. a certain number of lines to be connected, while the present invention can be modified to cover a wide and still expandable size range.

According to the present invention, an economically small switching field can be built, e.g. on a few hundred lines, because there is no certain number of steps required to implement such a small field. The field structure does not set any upper limit for the expansion of such a small field, i.e. the field can be easily expanded from a few hundred lines requiring a small number of steps to large line numbers requiring numerous steps, e.g. 50,000 lines. A small field in operation can also be expanded into a large field of operation without the re-cabling required by prior art systems.

The present invention provides a continuously expandable switch having one or more switch stages consisting of a plurality of selectors, each selector having two or more inputs and two or more outputs and adapted to reflect back traffic to any input of the selector to any other input of the same selector. , in which the outputs of the selector switches of the previous (but not the highest) stages act as reflection points of the traffic between the outputs of the selector switches of the same stage, and in which the other outputs of these previous stage selectors are connected to the inputs of the next higher stage selectors for telecommunication equipment. In a preferred embodiment of the present invention, the outputs of each selector of the highest switch stage are used exclusively as reflection points for traffic between inputs of the same selector and are not connected to other selectors, and thus these outputs are available in switch network extension to switch even higher selector inputs, and some of the previous switch stage outputs have no connection to other selectors, i.e. they thus only act as reflection points for the traffic between the inputs of the same selector and 3 74181 are available as outputs for further expansions with additional selectors at the next higher switching stage.

The main object of the present invention is thus to provide a substantially continuously expandable switch field.

It is a further object of the invention to provide an expandable switch field in the expansion of which it is not necessary to change the external or internal connection loops.

It is a further object of the invention to provide a multi-stage switch field in which the outputs of the switching elements of each stage are connected only to the switching limits of the higher stages.

It is a further object of the invention to provide a multi-stage switch field in which incoming traffic enters the field only the distance required to make the necessary connections.

It is a further object of the invention to provide a multi-input switch element which can be connected to a plurality of outputs, which is capable of mirroring the traffic arriving at any of its inputs back to any other inputs and is capable of connecting any input to any output.

It is a further object of the invention to provide a PCM switch module which can be continuously expanded without re-cabling over a wide range (large number of terminals to be connected) of 100: 1 or more and which can be implemented as a group switch, hub or deconcentrator.

It is a further object of the invention to provide a PCM switch that connects any time slot of any multiplex line to any other time slot of any other multiplex line.

It is a further object of the invention to provide a combined state and time switch module that connects a four-wire connection on both the forward and reverse paths.

It is a further object of the invention to provide a combined state and time switch module with path selection control, to which control commands can be introduced via a voice path, whereby no special control paths are required.

4 74181

The above and other features and advantages of the invention will become apparent from the following more detailed description of the preferred embodiments with reference to the accompanying drawings.

Drawings in brief:

Figure 1a shows a connection switch using simplified mirror point technology according to the prior art.

Figure Ib shows the prior art use of mirroring and switching verticals in a prior art switch field.

Figures 2a to 2d show simplified switch-field structures illustrating the field extensibility of the mirroring technique of the present invention, showing switch fields of one block (2a), two blocks (2b), three blocks (2c) and eight blocks (2d).

Figure 3 shows a mode switch on the input side of a slot change, which also uses a mirroring technique.

Figure 4 shows blocking as a function of the number of switch stages at different traffic intensity levels.

Figures 5a and 5b show the expansion of a switch matrix using mirroring / switching outputs; 5a shows one switch module and 5b an extended switch module.

Figures 6a to 6e show an extension of a multi-stage switch field according to the invention.

Figure 7a shows the complementary delay of a four-conductor road.

Figure 7b shows the control logic of one entry or exit point.

Fig. 7c shows an equivalent logic representation of the control logic of Fig. 7b.

Fig. 8 shows a four-wire delay line time switch control circuit using the switch logic of Fig. 7b.

Figure 9 shows a logic and block diagram of a field switching point.

Fig. 10 shows the switch point of Fig. 9 in the switch field matrix.

Description of the preferred embodiments:

Mirror point technology has been used in prior art Al coordinate switch fields, e.g. in a split switch by connecting two horizontal lines together vertically. This is shown in Figure 1a, in which the traffic of the line units 10 and 12 is connected to the connection switch 14 by horizontal lines 16 and 18 to the vertical line 20. Each of the line units 10 and 12 may have, as is well known in the art, a small coordinate switch circuit having a plurality of input / output lines 15 are connected. Mirroring is accomplished by connecting the traffic of the line 16 to the connecting switch 14, where it is mirrored from the vertical line 20 and exits the switch 14 via the horizontal line 18.

Fig. Ib shows an improvement on the prior art technique of Fig. 1a, which shows the mirroring principle used in the ESR-1 PABX switch field of Standard Elektrik Lorentz AG. In this system, the vertical conductors are connected between the switch modules at the same circuit hierarchy level, so the maximum field expansion size is limited. The line units 22, 24, 26 and 30 are thus connected to horizontal lines 32, 34, 36 and 38, which are connected to the switch modules 40 and 42.

Module 40 connects wiring units 22 and 24 by mirroring, module 42 connects wiring units 26 and 30 by mirroring, and modules 40 and 42 together with loop 44 connect wiring units 22 and 24 to units 26 and 30.

The numerals (1) on lines 32 and 34 correspond to the module switching of the traffic on lines 32 and 34. In this state, the switch points 46 and 48 are closed. The numerals (2) on lines 34, 38 and 44 correspond to the module switching of the traffic on lines 34 and 38. In this state, the switch points 48 and 50 are closed and the switch point 52 is open.

In the prior art system shown in Figure Ib, which uses the basic mirroring technique, the vertical conductor of one switch is connected to another switch at the same level in the circuit hierarchy, i.e. the same switch stage, which limits the maximum expansion size of the switch field. It has been found that - in contrast to the prior art systems described above - when connecting mirror / switching vertical lines according to the present invention only to higher level Switches with mirroring / switching vertical lines, a continuously expandable switching field is provided.

As used herein, the terms input, output, input, and output are defined as follows. The input is the port of the switch or group of switches that brings signals from the outside of the switch to it, and the output is the port of the 74181 6 switch that takes signals from the switch. An input is a switch interface that has both an input and an output port that carry signals in two directions associated with a duplex connection and are connected to one side of the switch. An output is a switch interface that has both an input and an output port that carries signals in two directions associated with a duplex connection and that is connected to the input side of the switch on the opposite side.

Figures 2a-2d show a mirroring rotary switch field which serves as an example of a mirroring / switching technique according to the present invention in which the output of any switch of a particular stage is never connected to the same or lower stage and the numbering of stages increases from the end stage to the pivot point.

It is to be understood that this switch field has been greatly simplified to expose its extensibility. Each switch matrix has a certain number of depths, ranges, i.e. switch steps through which the path connecting the two terminals must pass. In an inverted field, the switching path passes through each step only once and the path from the start to the end passes through each step in only one direction at a time. In the reversal field, the connection path between the start terminal and the end terminal can pass through any step in either direction and pass through at least one step at least twice, once in both directions.

In the present invention, the outputs of the stage with the highest number are used as mirror points, however, these outputs can always be connected to an even higher number stage without circuit changes. The outputs are thus used to connect to another switch, i.e. they can be considered as pivot points. The pivot point can be defined as the point in the pivot switch field where the signal connected through the field changes direction, i.e., stops moving towards higher steps. In addition, the mirror's mirroring and switching capability can be used in shift connections.

Figure 2a shows a 2x2 wire switch with two inputs, 100 and 102, and two mirror points, 104 and 106. The mirror ports 104 and 106 are also vertical connection wires, as described below. If each of the inputs 100 and 102 is a 24-channel time division multiplexed line, the switch 108, at a suitable concentration, as is known, could cause 150 lines to be connected to one input and the other input to a maximum of 24 trunks that can be fully interconnected, such as described below. Another example of the mirroring / switching technique is the case where a circuit with six lines is connected to the input 100, while a two-way transmission line enters the input 102, which goes to the second switching location analogously, i.e. as a non-multiplexed implementation. By using only one of the mirroring ports 104 and 106, one call is connected at a time, either from line to line or line to line. This field can be continuously expanded, e.g., to 12 lines and two main lines, as shown in Figure 2b, by adding switches 110, 112, and 113 to switch 108, thereby expanding to two stages. The added second terminal switch is denoted by the number 2 for this representation. When channel switching is required in the switch 108, its outputs 104 and 108 are used as mirror points, i.e. for calls between the original lines and the long lines. The mirroring capability of switch 108 is utilized while calls are also connected between new switches in a similar manner. However, in calls between wires connected to switch 108 and wires connected to switch 110 (to which as many wires and remote wires as switch 108) are connected, the outputs of switches 108 and 110 (i.e., the first two stages) are switched through the same second stage switch, either switch 112 or switch 113. The connection is established at the second stage mirror points 114, 116, 118 and 120. Thus, it can be seen that in the connections between the channels, i.e. the first switches 108 and 110, one output of each switch is used as a switch port to a common higher stage switch, the other output is used as a mirror port.

Figure 2c shows the expansion of the switch field to three primary switches and Figure 2d to eight primary switches. This expansion technique, which does not change the arrangement of the internal or external switching loops, can be achieved in space and time division switching and with a basic switching member of any size; Figure 2 shows a space division application. The block of three primary switches 8 741 81 shown in Figure 2c again provides six additional wires and again one bidirectional long-distance wire thanks to the third switch block 126. Of the traffic coming to switch 126, two out of three are statistically directed to the second primary switches 128 and 130 because two-thirds of the wires and intermediate wires coming into the switch field are connected to these. However, since each input constitutes one traffic unit, two-thirds of the switching units 128 and 130 represent four-thirds of the traffic units, which exceeds the traffic capacity of one of the switching outputs; therefore, two second stage switches 132 and 134 are reserved for the third primary switch 126. As can be seen in Figure 2d, the addition of the fourth switch unit does not cause a reorganization of any existing link. The second stage switch blocks 136 and 138 and the third stage switch blocks 140 and 142 are topologically similar to the primary switch blocks. Figure 2d shows an example of field expansion, without rearranging existing loops, into eight primary switch blocks, each of which comes with six wires and one two-way remote wire. The eight primary switch blocks 150 to 164 of the first stage of the switch field may be topologically identical to the switch units of Figures 2a to 2d. Compared to a single-stage reversal field, the switch field of the present invention is more economically expandable because the cost of a single-stage reversal field as switching points increases linearly as the number of terminals increases, i.e. the number of input ports or lines increases, while this field increases (expressed as 2 base logarithm. This is shown in the table below for the eight-block field of Figure 2d.

Primary- Added Field Field switches N (= stage blocks switches switches per primary block number - 1) total 111 1 0 2 3 4 2 1 3 5 9 3 4 3 12 3 2 5 7 19 3,8 6 5 24 4 7 5 29 4.1 8 3 32 4 3 16 80 5 4 32 192 6 5 9 74181

The switch blocks added to the field in steps 2, 3 and 4 are marked with numbers corresponding to the adding a primary switch block, which requires adding a correspondingly higher step. For example, the addition of the fifth primary switch 158 causes the addition of the second stage switches 166 and 168, the third stage switches 170 and 172, and the fourth stage switches 174 and 176.

Figure 3 shows the characteristic curves of one switch member of the preferred embodiment. The entire switch field consists of a number of such switch members. Each switch element must act as a status switch capable of connecting m input terminals to n output terminals. In addition, each switching element must have at least one time slot switching unit (TSI) for each input or output, where m is the number of input terminals and n is the number of output terminals. This marking of inputs and outputs is by way of example only and the number of TSI units corresponds to the lower of m and n. Even if a number of TSI units equal to or greater than the lower of m and n is used, the field would still be operational, albeit at an even lower efficiency. In addition, each switching element must have signal mirroring switching ports, which is essential for a four-wire network. In Figure 3, the switching / mirroring ports are shown in simplified form; however, it must be understood that each the ports correspond to the logical implementation shown in Figure 7a. There is also a need for a state switch capable of switching mx n. A concentration where m is greater than n and an expansion where n is greater than m can be implemented. If an additional symmetrical switch (nxn) is desired in the concentration case, only n of the m inputs need to be used. , because the inactivity of the remaining inputs only causes a small number of cheap ports not to be used. In addition, an m x 2n switch can be implemented by connecting the inputs of the necessary additional switches to inputs 234 and 236. Of course, the value of m can vary greatly: m can be any number of input terminals and n any number of output terminals.

Figure 4 shows blocking N as a function of the number N of switch stages at four loop levels. The term inhibition is defined for the purposes of this representation as the inability for any reason to connect _ - 1. ____ 10 74181 interconnected free wires or trunks.

An unobstructed field here means a field where at least one path, i.e. a link, is always available between any pair of free wires or trunk lines connected to the field, regardless of the number of paths already reserved.

Two important aspects of field operation are the field’s ability to respond to changing traffic levels and the effect of increasing the number of stairs on field field characteristics. When the number of field stages is increased according to the present invention (several switches are connected in each stage as a switching system, each operation is identical and parallel to the corresponding stage switch), the inhibition does not increase continuously but approaches asymptotically a certain value between zero and one and depends on the switch size and traffic intensity. The term traffic intensity is defined for this presentation as follows: the amount of traffic on one or more traffic routes per unit of time. Traffic intensity is generally measured in erlangs: one erlang is the traffic intensity of one continuously reserved traffic or the traffic intensity of one or more roads is one call per hour, one call per minute, etc. In the present invention, field blocking B at a certain number of switch stages N and low, medium and high traffic is that when the maximum inhibition level is reached with a certain number of switch stages N, the field inhibition no longer increases with increasing N, i.e. the curve describing the field inhibition as a function of N approaches asymptotically the maximum inhibition level. This is shown in Figure 4 for four traffic intensity levels: curve 1 shows low, curve 2 between low and medium, curve 3 between medium and high, and curve 4 shows high traffic intensity. As the switch size of each stage increases, the possibility of blocking decreases with a certain traffic intensity E.

Figures 5a and 5b show the expansion of the field with the mirroring / switching output terminal. The speech connections of the switch block 300 are provided by a time division state matrix 302 and exemplary handover units 304, 306, and 308. Each input (exemplified by 310, 312, and 314) and output (exemplified by 322, 324, and 326) has input and output connections along which and departure routes. The terms handover unit and slot change unit are interchangeable herein. Each switch matrix module 300 provides 32 channels to each of eight inputs, three of which are shown for simplicity: 310, 312, and 314 (corresponding inputs 0, 2, and 7).

The data at inputs 311, 313 and 315 of inputs 310, 312 and 314 (i.e. 0, 2 and 7) can be coupled to the inputs of handover units 304, 306 and 308 by a time switch matrix 302 at 316, 318 and 320. Thus, data at any of the switch module inputs can be selectively coupled to any inputs of the handover units during each channel time. Three handover units 304, 306 and 308, one of the switch module outputs 322, 324 and 326 shown for each, provide a predetermined delay and switch data from the input of one time channel to the output of another time channel so that no two channels are at the same time in any channel. For example, the information at the input 313 of the input 312 is connected via the switch point 354 to the input 244 of the input 318 of the handover unit 306. The information at the input 313 of the channel 15 is converted to the information at the output 328 of the channel 21.

Known units may be used in the handover units, e.g., those described in U.S. Patent No. 3,740,483; this patent refers to several references to time division. For example, in the present invention, the output 328 of the output 324 of the handover unit 306 may be forced into a second impedance state to switch to the output 330 of the handover unit 306 as shown in the figure. For example, handover may cause the information at the input 330 of the channel 21 to be changed to the information at the output 334 of the output 318 of the time channel 9. The switch 302 connects the output 334 to the output 338 of the data module input 314 via the switch point 340. This illustrates a data path corresponding to the two conductors of the four-wire. The other half of the data path is described as follows. The input 315 information of the time channel 9 input 314 is connected via the switch point 342 to the input 248 of the handover unit 306, the handover unit 306 switches the channel 9 information to the output 158 of the channel 15 input 314 and further switches the information via the switch point 350 to the input 152 of the channel 15 that 74181 12 of the switch matrix module inputs 310, 312, 314, etc. have independent access to the handover inputs in a predetermined manner.

Fig. 5b shows the expanded switch of Fig. 5a with a second traffic path example and its connections when several identical switch modules are connected as a multi-stage switch field. It can be seen that the input channel 15 of the input 2 of the module 300 forms a traffic path to the output channel 21 of the output 6 of the same module 300. The output 6 of the module 300 is connected to the input 0 of the module 300A. The input channel 21 of the input 0 of the module 300A is connected to the output 7 of the module 300A. to the output channel 30. The channel 30 of the output 7 of the module 300A thus forms a mirror point for this connection. The connection is complemented by the input channel 30 of the output 7 of the module 300A, which connects to the output channel 17 of the input 7 of the module 300A. The input 7 of the module 300A connects to the output 6 of the module 300B, which connects the input channel 17 of the output 6 to the output channel 9 of the module 300B.

This shows the connection of the input channel 15 of the input 2 of the module 300 to the output channel 9 of the output 7 of the module 300B by mirroring the output 30 of the output 7 of the module 300A. The return side of the four-wire connection is the complement of this switching period. The switching path selected through switch 300 shown in Fig. 5a before expansion is equally possible even after the expansion shown in Fig. 5b. Whether mirroring or passage occurs at the output 6 of the module 300 depends on the selected path. Thus, it has been shown that the switch module of Fig. 5a is modularly expanded in a multi-stage system by mirroring technology so that any necessary input switching can be made while leaving the mirror output free for further expansion, which is implemented by switching to a higher stage. The structure of the other switch modules 300C, 300D is similar to the above modules.

Figures 6a to 6e show switch fields in which each switch block consists of a 2x2 switch, and these switch fields are quantitative examples of the present invention. In practice, of course, larger switches of the order of 8x8, 16 x 16, 32 x 32, etc. can be used, depending on the structure, cabling and other economic considerations. If the 32 channels have 192 lines and the traffic intensity is 0.1 erlangs per line, each of these 32 channels has a traffic intensity of 0.6 erlangs. Assuming that 50% of the traffic is within the center, then long-distance traffic is 74181 13 19.2 erlang divided by two, i.e. 9.6 erlang per 192 lines. If long-distance traffic takes place in one direction in one group in each direction, each group of long-distance lines must be able to carry 4.8 erlangs on 192 lines. The table below relates to the time and space field of the present invention shown in Figures 6a-6e.

Pattern Lines Erlangia / Remote One-way Remote Remote Switch line traffic traffic lines lines mi (1% block total) 6A 192 19.2 9.6 4.8 11 22 1 6B 384 38.4 19.2 9.6 18 36 4 6C 576 57.6 28.8 14.4 25 50 7 6D 768 76.8 38.4 19.2 31 62 9 6E 960 96.0 48.0 24.0 37 74 12

The switch according to a preferred embodiment of the invention can be implemented in a single piece, combining both time and state switching, and these can be connected in a cascade so as to form a continuously expandable field with e.g. 2000-100,000 lines. Functionally, the handover portion of this switch can act as a delay line, which, whether implemented as a charge switching device (CCD) or a dynamic MOS shift register, causes the complementary delay required by the four-wire as shown in Figure 7a: input signals S1 (line 700) and S2 (line 702) have varying delays at S2 (lines 706 and 708) are typically 5-125 ms (signal S1 delay is shown by 709). The full-female delay 706 + 708 + 709 is typically 125 ms.

The implementation logic of this delay is shown in Figure 7b. Each entry and exit point of the signals is able to bring, take or connect the momentary signal through the switch.

The slot switching control signal C of line 710 is applied to AND gates 712 and 714 and to AND gate 716 via inverter 718. The digital speech signal S1 and the control signal are input to the AND gates 712 and S2 and the control signal to the AND gate 714. The digital speech signal S2 is input from the shift register 720 to the AND gates 714 and 716 and together with the inverted control signal to the AND gate 716.

741 81 14 The output signal of AND gate 716 (signal S2) and the output signal (SI) of AND gate 712 are applied to OR gate 722. Thus, either SI or S2 is connected to shift register 724. The simplified logic of Figure 7C shows shift registers 720 and 724 and the above logic 726. , and will be used in the following. When control logic is used at the input, the control signal of line 710 is the selected stored control signal; but when the logic is used at the output, the control signal is mirror control.

Figure 8 shows a time switch and associated control logic as shown in Figure 7b for a multi-channel four-wire system. The input signal S1 is applied to the input line 802 of the switch input 800, and the output S2, the return path of the four-wire connection, is taken from the switch input output line 804. The output 806 has an input line 816 and an output line 818. The delay of the signal S1 between input 802 and output 806 802, 808, 810, 812, etc., or other input points (not shown) from the delay line time switch with programmed control of the control memory 814.

The control memory 814 contains the addresses of the signal entry points in a predetermined and variable order. By giving the desired signal entry point from the control memory 814, the signal S1 is made to come and the signal S2 to leave the selected point of the delay line. The timing circuit 820 schedules the control memory 814 synchronously with the speech delay line so that the address to be selected for each S1 input is connected from the control memory 814 via line 822 to the serial-parallel register 824. 814 via line 822 to the serial-parallel register 824. gic port circuits reserved for 32 channels controlling input ports 802, 810, 812, etc. The figure shows these control signal logic port circuits as follows: 826 - channel 1, 828 channel 2, 830 - channel 3, 832 - channel 30 and 834 - channel 31. The parallel output of register 824 is applied to ports 826-834 via lines 836-844. Line 846 acts as the return line for mirror line 848 delay line. The synchronization signal applied to the timing circuit 820 synchronizes the speech sampling and the control code from the control memory 824. The two do not have to be bit synchronous, as the codes may be different: the speech sample may have eight bits and the control code five. Each of the signal input, input, and bypass switches 850, 852, 854, 856, and 858, located between its associated inputs and the output delays 860 to 870, causes the input and output points of the S1 and S2 signals to be selected so that the input and output of S1 between the required delay and the complementary delay corresponding to the return path of S2. The import, input, and bypass switch 848 provides signal mirroring at its output when the path selected between subscribers A and B requires a turn at this point in the field.

If desired, mirroring of a particular connection is accomplished by activating the control line of mirroring port 848 at an appropriate time. Example: a sample of the signal S1 is input to the input 802 of the input 800 and must be mirrored and returned from the output 804 of the input 800 at a predetermined later time, e.g., two channel times later than the signal S1 at the same channel time as the complementary signal S2 (which is signal sample in the other direction of the conversation) is applied to input 802 of input 800 and output 804 of input 800 as signal S2 30 channel times later, at the same channel time as the next SI sample is input to input 802. To do this, selection port 826 activates input / output logic 858 to bring SI to the delay line, and the mirror controller 872 of the mirror port 848 is activated one channel time later to mirror the S1 to the path 846.

The selection ports 834 are then activated to control the input / output logic 850 one channel time later to take the signal S1 and bring it as the S1 to the output 804 while the signal S2 is applied to the input 802 on the shift register delay line 862. When another 30 channel times have elapsed, the selection ports 826 reactivate the input / output logic 858 to receive signal S2X and output S2X from output line 804 as signal S2. Simultaneously with this, the next sample of the SI from the input line 802 is introduced into the shift register delay 870. Em. the switch thus transmits and mirrors the signals S1 and S2 as required by the switching path determined by the control memory 824.

Digitally encoded voice and control messages, which control the selection of switching paths of the switch modules and the handover delays that are switched by the switch module connections, are coded for each channel in 16 serial bits. Typically, 8 frames, 32 channels per frame, and 16 bits per channel are transmitted. The timing 16 741 81 ensures that, for example, channel 0 is in the same time window for both input and output. Channel switching allows the 16 bits of each channel to be transferred in a controlled manner to another channel by introducing a delay into the bitstream. This delay (for 32 channels) is a minimum of one channel period and a maximum of 31 channel periods. Mirroring is accomplished by changing the impedance switch outputs corresponding to each handover to a high impedance level and connecting the output and input of the selected channel handover output.

Fig. 9 shows a typical time division state switch point xy 900 of the time switch described above, which is the switching point of the input x including the input line 902 and the output line 904 and the output y including the input line 906 and the output line 908. One input of switch 910 is the switch selection signal from the control memory, the other input is the the output of the handover unit from line 906, and the output is connected to the input output line 904. The switch 912 receives a switch selection signal from the control memory and the signal of the input x input line 902, and its output is fed through the line 908 to the corresponding handover unit. Lines 906 and 908 can be connected at points 924 and 926 to input and output switches similar to switches 910 and 912 from up to seven other inputs. Input x input line 902 and output line 904 are also connected to gate detection overhaul fault detection circuit 914 and channel freedom detection circuit 916 with AND gates 918 and 920, the other inputs of which monitor port switching at desired times.

The gate detection and (redundancy) fault detection circuit 914 may be of conventional construction, and it detects messages directed to the control circuits associated with the output y of the input 902, checks the correctness of the encoding of these messages, detects the free channels of the input 902, and outputs signals to the output 904. or free space. For example, circuit 914 receives a "send busy" command from control circuits associated with output y, and the circuit then sends a reservation / fault message to line 904. When circuit 914 detects a selection request message from input line 902 to output y, it switches a priority selection signal to a switch point control circuit. than requests for output y of one input. The output of the channel freedom detection circuit 916 is connected to the free channel selection circuit 741 81 17 via line 922.

The matrix formed by the switch points xy shown in Fig. 9 is shown in Fig. 10, which shows one output 960 and its control as an example of possible eight outputs of input and 8 output matrices connected to two inputs, 962 and 964, of possible eight inputs 0-7.

The switching point xy corresponds to the switching point in Fig. 9. As shown with respect to Figure 9, eight such switching points can be connected to time switch (channel changer) 928 on lines 906 and 908. Time switch 928 is illustrated in connection with Figure 8. The gate detection, redundancy fault detection, and channel freedom detection circuits 930 and 932 operate in the same manner as circuit 914 of Fig. 9, and the channel freedom detection circuits 934 and 936 operate in the same manner as circuit 916 of Fig. 9. The outputs 922, 938, and 940 of gate detection circuits 914, 930, and 932 indicate that messages have been received in the respective circuits requiring a connection to the handover 928 and connected individually and separately to the switch point priority control circuit 942. When the circuit 942 receives requests from two or more lines simultaneously, the circuit selects one of these inputs and instructs to send busy signals to the other 9 unselected lines. , 946 or 948, as appropriate, to respective circuits 930, 914 and 932. These busy signals are applied to the respective output points of the switch point inputs as shown in connection with Figure 9. The switching point selection circuit 950 receives and stores on its control delay line, similar to the control memory 814 shown in Fig. 8, a switching point selected by the switching point selection circuit 942 for each 32 channel periods and opens and closes the selected switching point for each channel sequence, switching signals 95 to the control line 95. The signals at output 960 may include signals from a higher stage switch after mirroring that are identified by the aforementioned circuit 932. Channel freedom detection circuits 934 and 936 perform the same function as circuit 916 described in connection with Figure 9. It is to be understood that the matrix of Figure 10 is only an example. However, at points 966 and 968, seven additional matrices similar to those shown in Figure 10 may be connected to inputs 962 and 964. Up to six additional inputs can be implemented, 741 81 18 with circuits and connections similar to inputs 962 and 964.

Although the present invention has been described herein by way of a preferred embodiment thereof, it is to be understood that the spirit and scope of the invention as set forth in the appended claims include other embodiments, modifications, and applications that will be apparent to those skilled in the art.

Claims (8)

1. Expandable switching network with one or more switching stages, each of which comprises multiple switches, each switch having two or more inputs and two or more outputs and arranged to reflect traffic occurring at the heist of the other inputs. the same selector, and where the outputs from the selectors in a preceding switching step (though not of the highest order) act as reflection points for traffic between the inputs to the selector at the same switching step, and where the outputs from the selectors in the said preceding switching steps are connected to the following inputs higher order switching steps, intended for telecommunications and especially for telephone systems, characterized in that the outputs (114, 116, 118, 120 in Figure 2B) are assigned to each switch (112, 113 in Figure 2B; 140, 142 in Figure 2C) ) in a top-order switching step (step 2 of figure 2B, step 3 of figure 2C) is used exclusively as reflection points (RP) for traffic between the inputs to this selector (112, 113; 140, 142) and not connected to any other switches, and are thereby available for switching the inputs of switches in switching steps of even higher order if the network is to be extended, and that some of the outputs from the switches in the previous switching steps have no connection to other voters, ie that they only serve as reflection points for traffic between the inputs to the same selector and are available as outputs for further extensions with additional auxiliary selector in the corresponding higher order switching steps. Switching network according to claim 1, characterized in that when switching on auxiliary switch in a first switching step (110), switches are switched on in higher switching steps (112, 113). 3. A switching network according to claim 2, characterized in that, if necessary, the selector is inserted in an additional switching step which thus constitutes the highest switching step. 4. A switching network according to claim 1, characterized in that the switching network is a four-tree switching network and that each input (314 in Figure 5A) and each output (324 in Figure 5A) has one input (315, 330 in Figure 5A) and one output (328, 338 in Figure 5Λ), and that each input and output