FI73856B - SYSTEM FOER UTVAEXLING KODADE MEDDELANDEN MELLAN STATIONER. - Google Patents

Description

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SUOMI FINLAND

(FI) (21) Patent application - Patentansökning 801372

(22) Date of application - Ansökningsdag 28.04.8 O

National Board of Patents and Registration (23) Start date - Giltighetsdag 28.04.80

Patent- och registerstyrelsen (41) Publicly available - Biivit offentiig 05.11.80 (44) Date of publication and of publication - 31.07.87

Ansökan utlagd och utl.skriften publicerad (86) Kv. Application - United Kingdom (32) (33) (31) Privilege claimed - Begärd priority 04.05 · 79 France-France (FR) 79H319 (71) Compagnie Industrie] le des Telecommunications Cit-Alcatel, 12, rue de la Baume, Paris, France-France (FR) (72) Jean-Baptiste Jacob, Perros-Guirec, Yves Mathieu, Perros-Guirec,

Michel Ruvoen, Trebeurden, France-France (FR) (74) Oy Jalo Ant-Wuorinen Ab (54) System for the transmission of coded messages between stations -System för utväxlina av kodade meddelanden mellan stationer

The invention relates to a system for transmitting coded messages between stations and in particular, but not exclusively, between the operating units of a time division center.

Partial access systems for transmitting coded messages between stations are previously known. The stations can be computers, data transmitters and receivers, or more generally data processing devices. In such message transmission systems, a message with a higher priority than other messages has priority over these, which requires very expensive and complex equipment.

It is an object of the present invention to provide a system for transmitting coded messages which is simpler than known systems.

The present invention thus relates to a system for transmitting coded messages between stations, each station comprising an interface module connected to a signaling bus and a data bus, which are serial multiplexed connections synchronized by a central timer unit, each interface module being allocated a signaling module. consisting of two time slots, one even and one unpaired time slot. In this coded message transmission system, the signaling and data buses are duplicated for reliability reasons, whereby signaling messages are transmitted simultaneously on both signaling buses and data messages on both data buses when messages are received from only one bus.

In such a coded message transmission system, faults are detected quickly without loss of messages. The status of each interface module is transmitted with each frame in the time portion of the frame allocated to it, and each interface module stores the states of all other modules, allowing time savings in message transmission if one of the interface modules is not in use.

More specifically, the invention relates to a system for transmitting coded messages between stations interconnected by a signaling bus and a data bus, each station being connected to a common timing unit and including an interface module connected to the data bus and the signaling bus, the buses being multiplexed, the buses being multiplexed. each station is allocated a temporal part of the signaling frame, the station interface module comprising means for calling another station by transmitting the number of the called station with its own temporal part, characterized in that the multiplex connections are serial multiplex connections, that in the signal frame each odd time slot and that each interface module has: - means for receiving a response, - means for transmitting a response in the time portion of the calling station upon receipt of the number transmitted from the calling station, - means for storing the data message and means for transmitting said message in the data bus frame, - means for receiving the data message and means for storing the message, means for transmitting an odd parity bit at the end of the message, and means for calculating a parity of the received data message consisting of the data message plus the odd parity bit, and means for transmitting a "correctly received" signal or a "parity false" signal, depending on the result of the calculation.

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The invention will now be described in more detail with reference to an embodiment shown in the accompanying drawings, in which: Figure 1 is a block diagram of a system according to the invention, Figure 2 is a single station block diagram of Figure 1 and Figures 3 and 4 show the signaling part and data part of Figure 2.

The system of Figure 1 includes stations marker stations MQ1 and MQ2, translator stations TRI and TR2, charging unit stations TX1 and TX2, multi-register stations MR1-MR5, a control station OC connected to a control and operation center, and a memory protection unit station DSF. The stations are interconnected by the signaling lines LMSa and LMSb and the data lines LMla and LMlb. All lines are bidirectional. The signaling and data lines have been duplicated for reliability reasons.

Stations of the conventional type include an interface module with a transmit amplifier and a receive amplifier for each signaling and data line. Each line is arranged as a two-way bus and allows each station to communicate with any station connected to the bus. Each bus forms a serial multiplexed connection that is synchronized by a central timer unit.

These lines connect the control station OC to other stations, each of which includes an operating unit, which may be a marker, a charging unit, a translator, a multi-register, a memory protection unit or a control unit, and an interface module.

Figure 2 schematically shows one of the positions of Figure 1. The station includes a function unit 1 which performs the intended function of the station (marker, charging unit, etc.), and an interface module 2 to which the function unit is connected via the internal data bus L1, the test signal bus LT and the address bus LA. The interface module comprises: a data receiver 3 connected to a data bus LM1 consisting of data lines LM1a, LM1b, a data transmitter 4 connected to a data bus LM1 consisting of data lines LM1a, LM1b, a signaling receiver 5 connected to a signaling bus LMSa, LMSb, - a signaling transmitter 6 connected to the signaling bus ____ to 73ι 73856 LMS consisting of signaling lines LMSa, LMSb.

Receivers 3 and 5 each contain two amplifiers, one for each line forming the bus. In a seam-like manner, transmitters 4 and 6 each include two amplifiers, one for each line forming the bus.

Both lines forming the bus are used for transmission. However, only the second line of the bus is used in reception when a changeover occurs as a result of detecting a parity error. The changeover is controlled by the function unit 1 associated with the interface module 2.

The interface module 2 has a data part related to the data bus LM1 and a signaling part related to the signaling bus LMS. Fig. 3 shows the signaling part of the interface module and Fig. 4 the data part.

Fig. 3, which shows the signaling part of the interface module, shows the signaling receiver 5 and transmitter 6 shown in Fig. 2. The state memory 10 is connected to the internal data bus L1 and receives from it the status of the operating unit associated with the interface module. The unit number memory 11, which is a parallel input / parallel output type register, is connected to the internal data bus Li and receives the function unit number n therefrom. A timing signal generator 12 is connected to the output of the unit number memory 11 and receives signals BT from the timer unit of the respective operation unit. The timing signal generator generates the timing signals used in the interface module. The timing signal CE is input to a parallel input / serial output type transmission register 13, the input of which is connected to the state memory 10 and the output to the signaling transmitter 6.

The interface module uses the signals defined below: -ti is a signal corresponding to one time slot with a duration of 3.9 us and a period of 125 us. The frame has 32 signals ti.

-Θ1, Θ2, Θ3, Θ4, Θ5 are signals with a duration of 780 ns, a period of 3.9 us, and mutual offsets of 780 ns.

-h1, h2 are signals with a duration of 120 ns, a period of 780 ns and mutual offsets of 300 ns with signal h2 in phase with signals 01-05, i.e. the rising edges of the signals coincide in time.

T1 is a signal with a duration of 3.9 us and a period of 7.8 us-

The signal T1 is in phase with the odd time slots t1, t3 ... t31 and thus has a value of 1 during these time slots.

The signal T1 is the complement of the signal T1 and corresponds to even time slots.

These signals are received from the timer unit of the operating unit.

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As will be explained in detail later, one even time slot t2n and one odd time slot t (2n + 1) are allocated for each function unit from the frame, where n is the number of the function unit. In the following, the notation NTI means the odd time slot of a specified operating unit and the NTI even time slot. The timing signal CE is given during the NTI and its duration is determined by signals 92,93 and Θ4. It is developed over an odd period of time allocated to each business unit.

The call number memory 17 is connected to the internal data bus L1, from which the number of the called control unit is obtained. Memory 17 is a parallel input / parallel output type register, the output of which is connected to one input of AND gate 18. The second input of the AND gate 18 receives the signal NT1.91.h2. The output of the AND gate 18 is connected to the input of a parallel input / serial output type transmission register 19, which register is controlled by the signal h1. The output of the transmission register 19 is connected to the second input of the AND gate 20, the second input of the gate of which receives the signal CE1, which is a timing signal corresponding to the even time slot NTI reserved for the operating unit, the duration of which is 91-94.

The output of AND gate 20 is connected to the second input of AND gate 21. The output of the AND gate 21 is connected to the signal transmitter 6. The signal h1 enters one input of the AND gate 22, and the signal Τ1.Θ2 enters the other input. Its third input is connected to the signal receiver 5. The output of the AND gate 22 is connected to the control input of the flip-flop 23, to which the signal +1 is applied to the second input and the reset signal to.91. The output of flip-flop 23 is connected via inverter 24 to the second input of AND gate 21.

The signal receiver is connected to the second input of the AND gate 25, which port is enabled by the signal ΝΤ1.Θ1. The output of the AND gate 25 is connected to the control input of flip-flop 26, to the second input of which flip-flop receives the signal "1".

The output of flip-flop 26 is connected to the second input of the AND gate 27 when the second input of the gate receives the signal t3l.95.h2. The output of the AND gate 27 is connected to the input of a flip-flop 28, which flip-flop provides a signal enabling transmission to the data portion CE2 (Fig. 4). Flip-flops 26 and 28 restore the signal on line LT3 provided by the "transmission ends" flip-flop shown in Fig. 4.

The signal receiver 5 is connected to a serial input / parallel output type state reception register 30, the output of which is connected to the second input of the AND gate 31 when the second input of the port receives the ___ .. TT "--- 73856 signal T1.91.h2. The output of the AND gate 31 is connected to the unit state memory 32 input, which status memory stores the status of the functional unit connected to each data bus IMI and signaling bus LMS (Figure 1) The output of the unit state memory is connected to the internal data bus Li OR the output of gate 33 is connected to the indication input of the unit state memory OR the other input of port 33 is connected and a second input to the counter 34 via the AND gate 44 for cyclic memory assignment.The AND gate 44 is enabled by the signal ΤΪ.Θ1.

The output of the signal receiver 5 is also connected to a reception register 35 of the serial input / parallel output type, which receives the call number sent by the second operating unit. The output of the receive register is connected to the second input of the comparator 36. The second input of the comparator receives the number of the function unit belonging to the interface module via connection 37. The number is fixed by threading. The output of the comparator is connected to one input of flip-flop 38. The 1 condition of the flip-flop 38 is connected to the second input of the AND gate 39 with the output of the gate connected to the signal transmitter. The second input of AND gate 39 receives the signal Τ1.Θ1. The input of the wait register 40 is connected to the internal data bus Li to receive a signal having a value of 0 when the function module of the interface module processes the message. The output of the wait register is connected to the second input of the AND gate 41 when the second input of the gate receives the signal T1.05.h2. The output of the AND gate 41 is connected to the control input of the flip-flop 38. The output of the wait register 40 is also connected to the second input of the AND gate 43, the second input of the gate being connected to the output of the flip-flop 38. The output of the AND gate 43 is connected to the control input of flip-flop 42, to the second input of which flip-flop a signal +1 is applied.

The output of the flip-flop 42 is connected to the second input of the AND gate 45, the second input of the gate of which receives the signal t31.95-h2. The output of the AND gate 45 is connected to a flip-flop 46, which provides a signal enabling reception to the CR data part (Fig. 4). Flip-flops 42 and 46 are reset by the signal on line LT1 provided by the "reception ends" flip-flop in Figure 4. The unit sets the flip-flop 38 to receive a response signal at the output of the AND gate 39 when the comparator 36 outputs the signal with a positive number of the received number and the fixed wired number 7 73856. When the flip-flop 38 outputs a signal, the wait register 40 provides a signal that provides an enabling signal CR.

Figure 4 shows the data part of the interface module. It shows the data receiver 3 and the data transmitter 4 of Fig. 2. A serial input / parallel output type register 50 is connected to the data receiver 3. Its output is connected to a reception memory 51, the output of which is connected to the data bus Li.

In the write mode, the receive memory receives addresses from the operation unit via the address bus LA via OR gate 54. In the read mode, the assignment is cyclic and is performed by a counter 52 via a jA gate 53, which is enabled by a reception CR signal from the flip-flop 46 shown in Fig. 3. The output of AND gate 53 is connected to OR gate 54.

The input of the transmission memory 55 is connected to the internal data bus L1 from which it receives the message. An address for writing a message is provided by the operation unit via the address bus LA via OR gate 58. In numerical form, memory assignment is performed cyclically by counter 59 via AND gate 57 and OR gate 58. The AND gate 57 is enabled by the transmission enabling signal CE2 from the flip-flop 28 shown in Fig. 3. The output of the transmission memory is connected to a parallel input / serial output type register 56 via an AND gate 60, which is enabled with every 16 bits of the message frame (frame consisting of 16 bit words) by a signal S from the timing signal generator shown in Fig. 3 when the interface module is allowed to transmit a message.

The register 56 is controlled by the signal h1 and its output is connected to a data transmitter 4 and two dividing circuits 61, the output of which is connected to the AND gate 62, which is enabled by the signal t31.03. The output of AND gate 62 is connected to data transmitter 4. The message to be transmitted contains 157 bits between to.01-t31.82. The register 56 sends it directly to the data transmitter 4. The circuit dividing 61 also receives the message and at the end of the message its output value is 0 or 1. This is transmitted to the signal transmitter at time t31.03 and forms an odd parity bit.

The data receiver 3 is also connected to the "transmission ends" flip-flop 65 and via the inverter 66 to the "not received correctly" flip-flop 67. These flip-flops are connected to the test signal bus LT on the respective lines LT3 and LT4.

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The data receiver 3 is further connected by two dividing circuits 68, the output of which is connected to the AND gate 72 enabled by the signal t31.05, to the "reception ends" flip-flop 69 and via the inverter 70 to the "parity error" flip-flop 71. The output of the AND gate 72 is connected to data transmitter 4 and gives a "correctly received" signal at time t31.95. Flip-flops 69 and 71 are connected on lines LT1 and LT2, respectively, to the test signal bus LT.

The operation of the interface module shown in Figs. 3 and 4 will be explained below.

Each operating unit can transmit to the signaling bus an LMS consisting of the lines LMSa and LMSb during a specified time interval. If the number of the function unit is n, the time part reserved for this unit contains 125 time intervals t2n and t (2n + 1) divided into 32 time slots.

The numbers of the business units are assigned in the specified order of priority. The time slots assigned to each function unit number are listed below: to, t1 not assigned t2, t3 marker MQ1 No. 1 t4, t5 translator TRI No. 2 t6, t7 charging unit TXI No. 3 t8, t9 multi-register MR1 No. 4 t10, t11 multi-register MR3 No. 5 tl2, tl3 multi-register MR5 No. 6 tl4, tl5 memory protection unit DSF No. 7 tl6, tl7 not assigned tl8, tl9 marker MQ2 No. 9 t20, t21 compiler TR2 No. 10 t22, t23 charging unit TX 2 No. 11 t24 t25 multi-register MR2 No. 12 t26, t27 multi-register MR4 No. 13 t28, t29 not assigned t30, t31 control unit OC No. 15.

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The structure of the data sent by the function unit in the time slots t2n and t (2n + 1) allocated to it is as follows: time interval t2n Θ1-Θ4: coded address of the called unit sent by the function unit n Θ5: bit indicating a request to send a message or a response to time interval t (2n + l) Θ1: response bit sent by function unit n when called, Θ2-Θ4: status of function unit n coded Θ5: exclusivity bit sent by function unit n to confirm the exclusivity of the task (memory area conversion in similar units'.

Each function unit transmits its status with each frame for the part of the odd time slot Θ2-Θ4 allocated to it.

Each interface module receives all transmitted unit status messages and stores them in the unit status memory 32 (Figure 3), which is loaded with the signal TT.01.h2. Memory assignment is performed cyclically by counter 34.

The state of the functional unit can be one of the six possible states encoded by three bits in the interval t (2n + 1) between Θ2-Θ4. These six modes are: -NES inoperative, information transfer not possible when the unit is disabled or under test -OPE in operation, normal mode where the unit is in use with any kind of information transfer possible -RES in operation on a limited basis, this code is sent by the unit that is used but which is reserved beyond a certain level. It continues to perform started tasks but cannot start new tasks except in certain special situations -INDO not available reserved, the business unit continues to run and complete ongoing tasks but does not start new functions -INDL not available free, the unit has completed all running tasks but cannot accept new tasks, -INIT initial setting in progress, active function unit copies from similar function unit.

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The status messages of the functional unit are coded as follows in time interval t (2n + l):

Θ2 Θ3 Θ4 STATUS

0 00 NES

0 01 OPE

0 10 RES

0 11 INDO

1 00 INDL

1 01 INIT

The messages are sent on the data bus (lines IM1a and LM1b) in a frame that is in phase with the LMS frame of the signaling bus. The message starts at to.91 and ends at t3 1.Θ2, which forms a 157-bit data field containing nine 16-bit words and one 13-bit word. The parity bit is determined when transmitting so that the number of ones contained in the message, including the parity bit, is odd. This bit is sent at t31.03. If the parity check at reception gives a correct result, the receiving operation unit sends a "Received correctly" code to the sending operation unit via the data bus LM1: t31.04 = 0 and t31 * Θ5 = 1.

The message transfer procedure is as follows:

The signaling is sent to the signaling lines LMSa and LMSb. Signaling is received from the signaling line LMSa or LMSb. Data is sent to data lines LMla and LMlb. Data is received from the data line LM1a or LM1b.

In transmission, the transmission of messages is monitored by the operation unit, which receives information from the "transmission ends" flip-flop 65 and the "not received correctly" flip-flop 67 in Figure 4. Based on the states of these flip-flops, the transmitting operation unit receives information on whether the message was transmitted correctly or incorrectly: - flip-flop 65 = 0, flip-flop 67 = 0: the called function has not responded, - flip-flop 65 = 1, flip-flop 67 = 0: the response of the called function is "moved correctly", - flip-flop 65 = 0, flip-flop 67 = 1: the response of the called function is "transferred incorrectly".

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The principle of inspection at the reception is the same as at the time of consignment. Based on the states of the "transmission ends" flip-flop 69 and the "parity error" flip-flop 71 (Fig. 4), the called function unit knows whether the message was received correctly or incorrectly: - flip-flop 69 = 0, flip-flop 71 = 0: message not received, - flip-flop 69 = 1 , flip-flop 71 = 0: message received correctly, - flip-flop 69 = 0, flip-flop 71 = 1: message received incorrectly.

Between t2n.01 and t2n * 04, the calling function unit n transmits the coded number of the called function unit via the signaling bus LMS, followed by a bit indicating the message type at time t2n.05: "request" or "response", provided that the signaling bus is free. To this end, the AND gate 21 of the transmitting operating unit (Fig. 3) is set to the inhibit state if the operating unit has transmitted the counter usbit at time t1. 01 before the time of the calling operation unit NTI, where NTI means the even time slot t2n allocated to the calling operation unit.

If the called function unit is ready to identify its own number (comparator 36, Fig. 3), it immediately sends a response bit in the odd time slot NTI, at Θ1.

Upon detecting this response bit, the transmitting operation unit transmits its message via the data bus LM1 in the next frame, adding the calculated odd parity bit. The receiving operation unit transmits the "received correctly" code via the data bus LM1 with the last two bits of the frame, and the transmission of the message ends when the transmitting operation unit detects this code.

Transmission Verification: Message Parity: In the event of a (odd) parity error, the receiving entity does not send a "received correctly" code to the sending entity, which also receives a "not received correctly" flip-flop 67 (Figure 4) indicating that the entire message transmission procedure from paging must be repeated.

-duplication of data and signaling lines: the switching of lines a and b is controlled at reception by the control unit OC or by the operating unit itself on the basis of transmission errors.

comparison of signaling lines LMSa and LMSb at reception: the comparison allows the detection of an erroneous transmission on the second line.

Transmission-Reception Comparison of 12 73856 Signaling Lines: This comparison is performed between the information received from the signaling line LMSa or LMSb transmitted at the logic level in the transmission time slot reserved for the operating unit.

The following are examples of transfer transactions between two business units. In all examples, the calling unit is the marker MQ2 and the called unit is the multi-register MR1.

a) Sending a message from marker MQ2 to multi-register MR1

The frame time slots tl8 and tl9 are reserved for the marker MQ2. Time slots t8 and t9 of the same frame are reserved for the multi-register MR1. The marker wants to send the message to the multi-register.

In the first frame, the marker reads the status of 32 multi-registers from the state memory of the units. If the multi-register is active, the number of the multi-register MR1 is loaded into the call number memory 17 and the message to be sent is loaded into the transmission memory 55.

During the next frame, the marker sends an invitation code (multi-register MR1 number) to the signaling bus. If the multi-register interface module is ready, it recognizes the paging code (comparator 36) and sends a response bit via flip-flop 38 and AND gate 39 to prevent further transmissions on the signaling bus.

It activates the multi-register flip-flop 46 to transmit a signal enabling the transmission CR to authorize the reception of a message transmitted over the data bus on the next frame. In the marker, the response bit received from the multi-register activates flip-flop 28, which provides a transmission enabling signal CE2 to enable assignment to the transmission memory 55.

The message is sent in the next frame from register 56 and the odd parity bit is sent through AND gate 62. The message is received in the multi-register reception memory 51 via register 50. The two-splitting circuit 68 calculates the odd parity. The "correctly received" code is sent to the marker via AND gate 72 via the data bus.

In the next frame, the marker reads flip-flops 65 and 67 set by the received correct code and releases its interface module from the transmission mode. The message is ready for processing in the multi-register.

73856 (b) Cases where the message has to be sent

There can be two cases: 1 / the multi-register is not available and 2 / the signaling bus is reserved by a function unit with a higher priority than marker MQ2.

1 / Multi-register not available

During the first frame, the marker reads the unit status memory 32 to determine the status of the multi-register and detects that the multi-register is not available. The marker must move its call as long as the unavailable state continues.

During one of the following frames, the marker detects, as a result of the units' state memory query, that the multi-register is available and the transmission procedure is performed normally as explained in the previous example.

2 / Signaling bus reserved

During the first frame, the marker detects that the multi-register is active and loads its interface unit call number memory 17 and transmission memory 55. In the next frame, the interface module would normally send an invitation code via . In particular, the AND gate 21 of the marker MQ2 is not enabled after the flip-flop 23 has entered the 1 state due to the response of the upper operating unit of the marker MQ2. The paging code can be sent to the multi-register MR1 only if the calling unit (marker) has a higher priority, i.e. when no higher priority operation unit has sent a call to the signaling bus and received a response reserving the signaling bus.

c) The interface unit of the called function unit does not receive

In the first frame, the marker detects that the multi-register is active and loads the call number memory 17 and the transmission memory 55 of its interface module. In the next frame, the interface module sends the call code of the multi-register. The multi-register interface module is not ready (wait register 40 is not activated) because the multi-register is processing the message. The comparator 36 recognizes the call but the response bit is not transmitted and the flip-flop 38 is not activated. The marker interface module repeats the call until a response is received.

7 3 8 5 6 14 d) Message received incorrectly

The message is sent during the first two frames as explained in the first example: sending the message from the marker MQ2 to the multi-register MR1. In the next frame, register 56 sends a message and AND gate 62 outputs an odd parity bit. The multi-register receives the message and calculates the odd parity (circuit dividing by two 68). The result of this calculation sets the "reception ends" flip-flop 69 to 0 and the "parity error" flip-flop 71 to 1. An error has occurred in the transmission and the multi-register interface module does not send a "correctly received" code via the signal bus at time t31.05 (AND gate 72).

Failure to receive the "received correctly" bit in the marker interface module sets the "transmission ends" flip-flop to 65 0 and the "not received correctly" flip-flop to 67 1.

In the next frame, the marker tests flip-flops 65 and 67 via test signal bus LT. Enabling the "not received correctly" flip-flop 67 allows an error message to be sent to the control unit OC. The multi-register MR1 tests the flip-flops 69 and 71 of its interface module via the test signal bus LT and sends an error message to the control unit, setting its interface module to the previous state.

The invention is not limited to telephone exchanges, as exemplified by a typical application. The interface module device can be used in connection with other types of functional units than markers, charging units, etc., without departing from the scope of the invention, the invention being generally applicable to message transmission between stations in all systems where information has to be transmitted between its stations, especially in telecommunication and computer technology.

Claims (8)

A system for transmitting coded messages between stations interconnected on a signaling bus (LMS) and a data bus (LM1), each station being connected to a common timing unit and including an interface module (2) connected to the data bus and the signaling bus, these buses being multi connections synchronized by a central timing unit, each station being allocated a temporal part of the signaling frame, the station interface module comprising means (17, 19, 6) for calling another station by transmitting the number of the called station with its own temporal part, characterized in that the multiplex connections are serial multiplex connections , that in the signaling frame each time part consists of two time slots, an even time slot and the following odd time slot, and that each interface module has: - means (5, 25, 26) for receiving a response, its time part, the called station and the means (27); 28) for authorizing the transmission of a data message, - means (38, 39) for transmitting a response on the time portion of the calling station upon receipt of the number transmitted from the calling station, - means (55) for storing the data message and means (4) for transmitting said message in the data bus frame, receiving means (51) for calculating the parity of the transmitted message and means (62, 4) for transmitting the odd parity bit at the end of the message, and - means (68) for calculating the parity of the received data message consisting of the data message plus the odd parity bit, and means (72, 4) for transmitting a "correctly received" signal or a "parity false" signal, depending on the result of the calculation, in the data frame following the message. A system for transmitting coded messages between stations according to claim 1, characterized in that the interface module further comprises: - means (13) for transmitting its status on a time slot allocated to it, and - means for receiving (30) and storing (32) the status of each other station; . A system for transmitting coded messages between stations according to claim 1, characterized in that the lower the station priority, the higher the time slot number of the signaling frame and the interface module further comprising means (22, 23) for receiving a higher priority response from the station called by the higher priority. time reserved for the station and to prevent the transmission of the data message. A system for transmitting coded messages between stations according to claim 1, characterized in that the number of the called station is transmitted in an even time slot of the time part reserved for the interface module. A system for transmitting coded messages between stations according to claim 1, characterized in that a bit indicating the nature of the message is transmitted in an even time slot of the time part reserved for the interface module. A system for transmitting coded messages between stations according to claim 2, characterized in that the status of the interface module is transmitted in an odd time slot of the time part reserved for the interface module. A system for transmitting coded messages between stations according to claim 1, characterized in that an exclusivity bit is transmitted in the odd time slot of the time part reserved for the interface module when the station wants to ensure the exclusivity of the task. A system for transmitting coded messages between stations according to claim 1, characterized in that the signaling bus and the data bus are duplicated, that the signaling message is sent to both signaling buses and received from the second signaling bus, that the data message is sent to both data buses and received from the other data bus. receiving a message with a parity error determines the switching from one bus to another. 17 73856