FI72019C - FOERFARANDE OCH SLINGSLUTNINGSKRETS FOER UTFOERANDE AV SLINGSLUTNINGEN AV ETT SLINGSLUTANDE FELLOKALISERINGSSYSTEM I EN DIGITALISK LEDARANORDNING. - Google Patents

Description

1 72019

The invention relates to a method and a looping circuit for performing looping of a loopable troubleshooting system of a digital line device, which line comprises terminal repeaters, a cable between them and a repeater connected to the cable at appropriate intervals , which, after receiving its address signal transmitted as code errors of the line signal, switches the line signal back to its input direction.

One method of troubleshooting a transmission channel for transmitting PCM signals is known, for example, from FI patent publication 61,977. controls the looping of each repeater. Thus, loop control is analog and the repeater has to use cumbersome and expensive tuned circuits.

Purely digital methods for performing looping are also known, in which looping is achieved by sending an address signal to repeaters as a coded digital codeword like a wire signal. Such a method in which the addressing signal is additionally transmitted as code coding errors of the 30 line signals is known from CH Patent Publication 608 151. Thus, the address signal uses repeaters in the same manner as a normal line signal, so that the transmission path length is not limited. However, a prerequisite for error-free operation is that there are no additional codewords from the Transmission Line for the 35 address periods.

2 72019

In order to eliminate the problems encountered in the known solution, it has been an object of the invention to develop a method for performing looping, by means of which the possibility of malfunctions is made extremely small.

This method according to the invention is characterized in that the characters of the address signal are transmitted in different time unit numbers of code errors of the line signal at a rate independent of the rate of the line signal.

In this case, the addresses are thus transmitted by means of code errors added to the line signal 10.

The line signal thus does not correspond to normal traffic. The second logical address character corresponds to a period with code errors and the second logical address character corresponds to a code error-free period.

15 At the time of address transmission, the control signal shall be selected so that the added code errors do not cause excessive degradation of the system performance compared to a code-free normal signal. During the measurement period, the signal can be freely selected.

The advantages of the solution according to the invention are extremely good reliability, because a malfunction with a normal error-free signal is not possible. In addition, the power consumption of the required looping circuit becomes small, since most of the circuits can operate at a low frequency because the timing is independent of the speed of the line signal.

The invention also relates to a looping circuit for looping a loopable fault locating system of a digital line, which line 30 comprises terminals, a cable between them and repeaters connected at appropriate intervals to the cable, the looping circuit comprising each repeater and the terminal means for detecting code errors in the transmitter signal, means for converting the pulses generated by the detector to a digital address signal, and control means for comparing the received address signals to the own address of said looping circuit and transmitting a control signal according to the result of the comparison. This looping circuit according to the invention is characterized in that the means for converting the pulses generated by the error detector into a digital address signal comprise an integrator for calculating the time unit number of pulses The implementation of the circuits included in the looping circuit allows them to be incorporated into a single microcircuit.

In the following, the looping method according to the invention and an exemplary pyrite embodiment suitable for carrying it out will be described in more detail with reference to the accompanying drawing, in which Figure 1 schematically shows a looping fault-locating system, Figure 2 schematically shows the repeater of Figure 1, and Figure 3 shows Figure 2 in more detail. included looping circuit.

In the looping fault locating system according to the present invention, schematically illustrated in Fig. 1, the fault locating is performed by replacing the wire signal with an output signal of the measuring device 1 incorporating the address code 30 of the looping repeater in the form of code errors. Then, in the system of Fig. 1 consisting of a Δ-station terminal repeater 2, a plurality of repeaters 32 (only one shown), and a B-station terminal repeater 2, the assigned repeater loops, transmitting the signal received from the A-station back in the A-35 direction. Based on the errors of the return signal, the quality of the operation of the system part 4 72019 in the loop can be determined. Proceeding in the chain towards the B position, a repeater is found in which the looped signal is erroneous and the fault is limited to one repeater interval. In the figure, the notation AIS means an alarm notification signal indicating the existence of a fault situation in the network.

Figure 2 shows in more detail the repeater 32 included in the system of Figure 1. The repeater according to Figure 2 comprises an input transformer 3, an operational amplifier 4 and an output transformer 5 for wiring pairs passing through the repeater 10 in both directions. The input line (upper line in Fig. 2) is a looping circuit 6 according to the invention connected between the operational amplifier 4 and the output transformer 5, with timing control crystal oscillator 7 and address selection field 8 as external elements, by means of which its own address can be set. In the exemplary embodiment, a 6-bit address is used, with 64 different addresses being transferred from the address selection field 8, which can be implemented e.g. by switches, in parallel to the loop-20 circuit 6. The output of the loop circuit is connected to the return line (lower pair in Figure 2). to a controllable switch 15 arranged between the system 3 and the operational amplifier 4, by means of which the information of the supply line can be looped into the return line.

Fig. 3 shows in more detail the looping circuit included in the repeater of Fig. 2, which is of course also included in the terminal repeaters 2 shown in Fig. 2. In the exemplary structure of Fig. 3, the error detector 9 receives a 2 Mbit / s signal as two data. the second (-) pulses, the error generator generates error pulses for each detected code error. The error pulses set the memory circuit 10 associated with the output of the error detector 9 to "1". The integrator 11 connected to the memory circuit 10 reads and resets the memory circuit 35 by a clock obtained from the crystal oscillator 7 via the timing circuit 12. Depending on the value of the memory 10, the integrator 11 11 5 7201 9 counts either up or down. When the value of the integrator is above the threshold level, the value of the data is at input 1, otherwise 0, of the receiver 13 connected to the output of the integrator. The control circuits 14 connected to the output of the receiver 13 form the loop (LP) and terminal (CT) controls on the basis of the received addresses, the own address set on the device and the forced control of the loop-10.

Each detected code error sets the memory circuit 10 to "1". The integrator 11 reads and resets the memory circuit 10. If the value at the moment of reading is "1", the integrator 11 decreases upwards if the "O" downwards. The limit values of the counter acting as an integrator are 0 and N. system immunity is significantly improved.

The character expression performed by the integrator 11 is followed by the reception of the entire address word. When the counter value of the integrator 20 is below the selected threshold value, the data value is interpreted as "0" and when the counter value reaches the threshold value, the data value is interpreted as "1". In this way, the receiver 13 receives a series of binary pulses, which it interprets as the address code of one of the repeaters and the associated al-25 characters and terminals. If several such address codes are received, e.g. 3 in a row, the control circuits 14 interpret the address as received, compare it with the address determined by the repeater's own address field 8 and give loop (LP) and terminal (CT) controls if the repeater's own address is received, and only the terminal if an address code of another repeater has been received. The loop control controls the switch 15 controlled in the connection of Fig. 2, causing it to move to the position shown in Fig. 2, whereby the signal of the input line (measurement-35 signal) is switched back in its input direction. Thus, it is returned to the measuring device 1, 6 72019 shown in Fig. 2, which, on the basis of the return signal, is able to determine whether the looped line section contains defective parts.

It should also be mentioned that the error detector of the looping circuit located in the terminal repeaters can replace the code error indicator included in the normal-5 terminals in the terminal repeaters.

Although the invention has been described in connection with only one exemplary embodiment, it is to be understood that the method of the invention for transmitting an address for controlling splicing in the form of code errors can be applied in many other ways within the scope of the appended claims.

Claims (5)

A method for performing the loop coupling of a loop-coupling fault locating system in a digital conductor device, said conductor device comprising final covers (2), a cable between the said and the cable connected at appropriate intervals (32), wherein in each cover (32) and end cover includes a loop switching circuit (6) which, upon receiving its address signal transmitted as the code signal of the conductor signal, switches the conductor signal to its input direction, characterized in that the address signal marks are transmitted as a different time unit number of the speed signal code error of the conductor signal by . 15 2. A method according to claim 1, characterized in that a code error containing cycle is transmitted to correspond to one logical signal of the address signal and a cycle without code error is transmitted to correspond to the second logical mark. 20 3. A method according to claim 2, characterized in that the address marks in the reception are divided into a plurality of time intervals, of which a digital integrator (11) forms the address marks by integrating upwards if the error amount during said time interval exceeds a set limit and otherwise downsized. Method according to claim 3, characterized in that, after identification of the address mark, the integrator is reset to improve the interference tolerance of the address mark transmitted without code error. A loop coupling circuit for performing the loop coupling of a loop coupling fault locating system in a digital conductor device, said conductor device comprising end covers (2), a cable between them and to the cable at appropriate intervals (32), each one of which covers (32) and end cover (2) input loop coupling circuit (6) upon receipt of its address signal