FI61773C - THERMOUS INTEGRATION THREADER THREADER - Google Patents

Description

rft1 ANNOUNCEMENT

1¾ (11) UTLAGG NINGSSKRI FT ^ ‘^ C Patent -nySnetty 10 09 1902 * ^ V! ^ ^ Patent meddelat ^ (51) Kv.lk?/lnt.CI.3 H 01 L 29/10

FINLAND —FINLAND (21) P »Wnttlh» k «mu * -Pu.ntt ™ öknlni 3U88 / TU

(22) HtkamlspUvt - An * 6knlng * dag 02.12.7 ^

^ ^ '(23) Alkuplivt — GiklghMidag 02.12.7U

(41) Been stuck - Bllvlt offuntllg OU. 06.7 5

Patent and registry holders .... ..... .... . .....

* (44) Nlhtlvlktlpwton | -

Patent and registration authorities Ansöktn utltgd och utl.skriftan public · red 31.05.82 (32) (33) (31) Privilege requested —Begird priorlt «03 * 12.73

Federal Republic of Germany-Förbundsrepubliken Tyskland (DE) P 23Ö0081.9-33 (71) Licentia Patent-Vervaltungs-GmbH, Theodor-Stern-Kai 1, 6 Frankfurt am Main, Federal Republic of Germany-Förbundsrepubliken Tyskland (DE) (72) Edgar Borchert, Belecke, Horst Gesing, Belecke, Rigobert Schimmer, Belecke, Federal Republic of Germany Tyskland (DE) (7U) Oy Kolster Ab (5U)

The invention relates to a thyristor comprising a monolithically integrated diode, wherein the thyristor and the diode have a common base layer, wherein the diode region consists of a part of the common base layer and two adjacent highly doped opposite conduction type edge zones, and a method of manufacturing the same.

Thyristors with a monolithically integrated diode are successfully used when it is necessary to connect a special diode in the opposite direction to the controlled rectifier, for example in horizontal deviation switches of TV receivers or in vehicle ignition systems or in some reversing switches. With such an integrated device, it is possible to replace two five-terminal components with a single three-terminal component.

A disadvantage of the known thyristors with a monolithically integrated diode is that an excessive dynamic emission voltage occurs when the diode is connected after the conistor has been connected. This excessive dynamic emission voltage results, when the component is connected as a rush switch to the horizontal deviation part of the TV set, image disturbances which appear as vertical bars (gray bars) on the picture tube. Such image disturbances can be eliminated, among other things, by means of the invention.

It is therefore an object of the invention to prevent these oversized dynamic pass voltages which occur when a diode is connected after the thyristor is commutated. In this case, the solution to the problem must be achieved either solely by increasing the lifetime of the charge carriers, which at the same time would result in an undesirably excessive thyristor recovery time, or by greatly increasing the diode surface, which would inevitably increase the component and naturally cause disadvantages. as a solution to the problem.

This problem is solved with the thyristor according to the invention so that the strength of the common base layer in the diode region is lower than the strength of the base layer in the thyristor region.

Suitably, the base layer of the diode is selected to be thinner than the base layer of the thyristor. If this base layer is an n-base layer, this can be achieved in such a way that either the p-zone bounded by the n-base layer or the n-zone bounded by the n-base layer, but possibly both are thicker in the diode region than in the thyristor region. In this case, the difference in thickness of the two n-base layers of the diode and the thyristor is determined such that, on the one hand, the dynamic emission voltage of the diode decreases substantially, but on the other hand, so that the diode breakdown voltage is not below the thyristor zero-tipping voltage.

The invention achieves that, just as in a separate component, also in an integrated component, it is possible to prevent the diode breakdown voltage from falling below the zero tip voltage of the thyristor, although the n-base layer resistivity increases, which is possible and also used in Namely, since in the integrated structural element both the basic layers of the thyristor and the diode form a common interdependent zone, they also have a similar conductivity alloying, which excludes local 3,61773 conductivity changes.

the resistivity of the n-zone is adjusted to the value required for the required zero tilt voltage of the thyristor. In this case, in the same n-base layers, the breakdown voltage of the diode is above the zero-tilt voltage of the thyristor and as the layer thickness of the n-base zone of the diode decreases, its break-through voltage also decreases, so that it may eventually fall below the zero-tilt voltage of the thyristor. According to the invention, the n-base band of the diode is now reduced so far, or the difference in thickness between the thyristor and the n-base zone of the diode is adjusted so that on the one hand the desired dynamic output voltage reduction is achieved but on the other hand the diode breakdown voltage is not below the thyristor zero voltage. The breakdown voltage of the component shall not be reduced when the field strength is exceeded more than is permitted. Otherwise, the intermediate zones of the diode must not be so thin that an undesired decrease in the load current occurs, because this - when using a structural element in TV sets - brings with it additional interference to the picture, the so-called black bars.

The accelerated generation of charge carrier density in the n-base zone of the diode, with the reduction of the layer thickness, also has an effect on the further increased lifetime of the charge carriers in this region. On the other hand, the lifetime of the charge carriers in the thyristor and diode region must not fall below a certain maximum value due to the required low recovery time of the thyristor and the required low inhibitory delay time of the diode. Therefore, it is necessary to add to the conductivity alloy with which the desired layer sequence of the structural element is made a life time alloy to reduce the life of the charge carriers.

Lifetime doping is performed in a known manner by insulating gold diffusion. With the structural element according to the invention, the diode base layer is thinner than the thyristor base layer, but the diode-n + layer is thicker than the thyristor-n + layer, a favorable local charge carrier lifetime distribution in the common base layer is achieved so that the diode region carriers have a longer lifetime.

It is known that the solubility of gold shows higher values in high-alloy zones, especially in the n-conductor type zones 4 ". Therefore, the lifetime of charge roofs in the region of the n-base layer bounded by the n-zone is larger than in other sub-zones. is substantially thicker than the n + layer of the thyristor - the emitter zone also acts more strongly as a binder than this with the same center doping, thus the lifetime of the charge carriers is higher in the diode region than in the thyristor region.

However, since, on the other hand, it has also been found that too long a lifetime of the charge carriers in the diode region leads to an unfavorable diode blocking operation, the additional increase in the lifetime of the charge carriers according to the invention is reduced. The advantage of gold diffusion is based on the fact that with this insulating method step, as described above, it is possible to set both the lifetime height of the charge bases in general as well as its difference in adjacent layers to a predetermined value.

An essential part of the invention is also a method for manufacturing a thyristor such as the one described above, which method is characterized by the following steps a) coating an n-conductor semiconductor wafer with oxide layers and screen printing or diffusing from a phosphorus nitride source to provide an n + layer in the first diffusion; in the third diffusion.

This method is explained in more detail with a few embodiments and - partly schematic - drawings in which Fig. 1 shows a semiconductor feedstock plate, Fig. 2 shows a method in which an open diode ring is formed on a semiconductor wafer, Fig. 3 shows a semiconductor wafer after a first diffusion, Fig. 4 shows a semiconductor wafer after 51717, Fig. 5 shows a finished semiconductor wafer after a third diffusion, Fig. 6 shows a semiconductor wafer from which the structure of Fig. 1 has a diffused β-layer, Fig. 7 shows the structure of Fig. 6 after a new diffusion, and Fig. 8 shows a second final composition of the semiconductor wafer.

To carry out the process, one starts from a semiconductor wafer 1 in Fig. 1, for example an n-conductor type silicon wafer with a layer thickness of approximately 210 .mu.m, the first surface of which is first provided with dense and thick oxide layers 2 and 3 by 16 hours of oxidation at approximately 1200 ° C in moist oxygen. .

According to the method of the known semiconductor technology, the oxidation layers 2 and 3 are now covered with layers 4 and 5 by photocolor or screen printing technique, leaving areas free where the oxidation layer is removed by further treatment with hydrofluoric acid or a solution containing hydrofluoric acid. In this case, a structure with an open diode ring 6 is provided, as shown in Fig. 2.

The photoc lacquer or screen printing lacquer layers 4 and 5 are then removed as a solvent, and in the first diffusion, by phosphorus nitride diffusion from a phosphorus nitride source in a sealed quartz ampoule at a temperature of about 1250 ° C, an n + layer 7 is obtained as shown in Figure 3. The diffusion time depends on the layer thickness of the semiconductor material and the specific requirements for the second and third diffusions, which immediately follow the first and are explained below. The diffusion time of the first diffusion should preferably be chosen so that the structure according to Figure 5 is obtained after all the diffusion steps. In the example described, in which the plate thickness of the starting material was about 210 μm, an n + layer 7 with a layer thickness of approximately 60 to 70 μm is obtained in about 50 hours.

In a second diffusion with a gallium phosphide source, a structure according to Figure 4 with p-conductive layers 8 and 9 is obtained in about 10 hours at a temperature of about 1250 ° C. 3 6 18 -3 38 .. .42 groove and interference site density (3.5 ... 5.9) * 10 atoms'cm, 18-3-j- preferably 4.5 * 10 atoms * cm. The highly doped n layer 7 is virtually unchanged by the small amounts of gallium atoms diffused in.

corresponding to the concentration and depth of penetration of the β-layers 8 and 9 after the second diffusion is prepared - as shown in Figure 5 - in a third diffusion associated with the opening of the cathode ring 10, in approximately 8 to 15 hours, preferably 12 hours, at 1250 ° C, from the gallium phosphide source in the same way as in the second diffusion, the n + layer 11. In this case, the dopant diffused both in the second diffusion and also the n + layer 7 formed in the first diffusion further deeper and form the structure according to Fig. 5. The private layer thicknesses after the third diffusion are, n + layer 7 approximately 80 ... 90, n + layer 11 approximately 30 and p-layers 8 and 9 approximately 60.

In this case, the difference in layer thicknesses (x-y in Fig. 5) between the basic zones 14 of the thyristor and the diode is quite significant, and the given magnitude range gives a preferred embodiment of the invention. In the first example shown, this difference is mainly 20 to 30.

Since this method results in excellent accuracy and reproducibility of diffusion results, it also provides ideal starting points for gold diffusion which is very strongly dependent on the diffusion results, which in turn has proved particularly suitable for obtaining structural elements suitable for too high frequencies.

For this gold diffusion, the plates from the second gallium phosphide diffusion are treated to remove the oxide layer with 40% hydrofluoric acid for approximately 5 minutes. In the subsequent surface hardening process, a uniform gold layer is separated from the gold solution, which preferably contains approximately 10% by weight of gold in 1.5 normal hydrofluoric acid solution. The gold is then diffused inside during approximately a pound, at a temperature of 800 to 950 ° C, preferably between 870 and 875 ° C.

In another example, a silicon semiconductor wafer having a thickness of approximately 180 is used as a starting material. The n + layer 7 7 61773 is obtained in about 50 hours at a temperature of about 1250 ° C, using arsenic as a dopant. Instead of the two, second and third diffusions described in the first example, a single double diffusion of gallium arsenide is produced here as an alloy in about 20 hours at 1250 ° C, the layer sequence of Figure 5, where f are the individual layer thicknesses, n layer 7 is approximately 65 ... 75 μm, n + layer 11 approximately 20 μm and p-layers 8 and 9 approximately 45 μm.

In a further formulation of the method according to the invention, as shown in the first example and illustrated in Figures 1 and 2, the silicon wafer 1 is provided with oxide layers 2 and 3 and silk-screen or photoc lacquer layers 4 and 5. Unlike the first example, an n + diode ring is not opened 12 - as shown in Figure 6 - the oxide layer is removed and followed by subsequent boron diffusion over 34 hours at a temperature of about 1250 ° C, a p-layer 13 having a layer thickness of about 60-70 after the first diffusion. Thereafter, the oxide layer 2 is again closed in the diode region 12 and opened in the region 6.

Now in the following diffusion with gallium phosphide as an alloying agent carried out for 10 hours at a temperature of about 1250 ° C, an n + layer is formed - as shown in Fig. 7 - and both p-layers 8 and 9 with a thickness of approximately 40 μm. During these two diffusions, the diffusion fronts of the p-layer 13 also pass further, as a result of which its layer thickness increases to 70 to 80 μm.

In the third diffusion associated with the cathode ring 10, an n + layer 11 is obtained from the gallium phosphide source at a temperature of about 1250 ° C for about 12 hours, whereby again the fronts of the above-mentioned diffusions continue to run. Finally, the sequence shown in Fig. 8 is obtained, in which the individual layers have approximately the thicknesses shown below: n + layer 7 50 μm; p-layer 8 30 μm; p-layer 9 60 μm; n + layer 11 30 μm; p-layer 13 75 ... 85 μm. Thus, for the invention, the o-plane difference in layer thickness of the n-base layer 15 in the thyristor and diode regions x-y is thus obtained in this case by increasing the thickness of the p-layer 13, whereas in the first example this returns to the increased thickness of the n + layer 7.

Claims (11)

A thyristor containing a monolithically integrated diode and in which the thyristor and the diode have a common base layer (14, 15), the diode region (y) consisting of a portion of the common base layer (14, 15) and two adjacent high-doped edge regions (7, 8, 13) of the opposite conductor type, characterized in that the thickness of the common base layer (14, 15) in the diode region (7) is less than the thickness of the base layer (14, 15) in the thyristor region (x). 2. Thyristors according to claim 1, characterized in that the common base layer (14, 15) is n-conductive. 3. Thyristors according to claim 2, characterized in that the reduction of the layer thickness in the common n-base layer (14) in the diode region can be compensated by an increase of the layer thickness in the n + * conductive edge region (7) of the diode. 4. Thyristors according to claim 2 or 3, characterized in that the reduction of the layer thickness in the common n-base layer (15) can be compensated by an increase in the layer thickness in the p-conducting edge region (13) of the diode. 5. Thyristors according to any one of claims 2 ... 4, characterized in that the common n-base layer (14, 15) has a longer service life for the conductor carriers than within the thyristor region. 6. Thyristors according to any one of claims 1 to 5, characterized in that the semiconductor body is of silicon. Process for the production of a thyristor according to any one of claims 2 to 6, characterized by the following steps: a) the coating of an n-conductive semiconductor disc (1) with the oxide layers (2) and (3) and with silk printing or photo lacquer layers (4) and (5), b) opening a diode ring (6) in the oxide coating layer by acid treating with hydrofluoric acid or with a solution containing hydrofluoric acid and the phosphorus transferring.