FI58238C - FOERFARANDE FOER ETT PAO MOTTAGSSIDAN SEPARERA BINAERA SIGNALERINGSTECKEN FRAON EN SERIE AV TIDSMULTIPLEXSIGNALER SAMT KOPPLINGSANORDNING FOER UTFOERANDET AV FOERFARANDET - Google Patents

Description

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Vs (51) K ».ik.Vci.3 H 04 J 3/12 FINLAND — FINLAND (21) Pttinttihrtemu · —taMWamekning 2028/73 (22) KUkwnl« pUvt — Amttknlnpdac 25.06.73 (23) Alkupllvt — GlMghvtadac 25.06. 73 (41) Interpreters (ulkMol - Bllvlt effwcHg 28.12.73 PMMttl · J »Registry Board NllKMtolpe ™). kuUiulk ^ un pum.-

Patent · och registerstyrelsan '' AmMcm uthgd och ucukriten puMicarad 29.08.80 '(32) (33) (31) Prr * »« r «TuoUceu * —Begird prloritet 27.06.72

Switzerland-Switzerland (CH) 96U6 / 72 "(71) Siemens-Albis Aktiengesellschaft, Zurich, Switzerland-Switzerland (CH) (72) Josef Fluhr, Ami / AG, Eduard Rentsch, Thun, Dieter Schupp,

Zurich, Switzerland-Schweiz (CH) (7 * 0 Oy Kolster Ab (5 ^) Method for separating binary signals on the receiving side with time multichannel signals from a series and a switching arrangement for implementing the method - av förfarandet

The present invention relates to a method for separating binary signals on the receiving side by time multichannel signals from a series, wherein in a pulse frame having several time slots, k are information channel time slots and at least one signaling time slot, n signals are transmitted for p information channel time slots and signals for all information channel slots. signaling time slots in the superframe structure as well as the switching arrangement for implementing the method.

In time multi-channel transmission devices, in addition to the actual data transmission, signals are transmitted. According to the proposal of the Commission of the European Postal and Telephone Administration (CEPT), a time slot of 0 for each frame structure is used for 0 frame locking, time slots 1 to 15 and 17 to 31 for source code information channels and time slot 16 for signaling transmission. for two of the 30 information channels. In addition, within the superframe structure comprising 16 frame structures, the 16th time frame of the 0th frame structure for multi-frame locking, the 16th time slot of the 1st frame structure for half 1. and 17 · the transmission of information channel signals, the 16th time period of the 2nd frame structure for half of the 2nd and 18th .for the transmission of information channel signals, ... etc., and the 16th time period of the 15th frame structure for the transmission of 15th and 31st information channel signals.

With eight hits per time slot, four hits are available for each information channel for the simultaneous transmission of four independent signal states, with each signal state being sensed every 2 ms with a frame structure length of 125 f * s.

The invention solves the task of finding a method according to which the signals transmitted in the signaling time slots are demultiplexed (decomposed) and can likewise be directed to the demultiplexed information channels.

Method according to the invention, characterized in that the signaling of each individual signaling time slot n is fed in parallel to the memory line of the memory matrix ~ and both ·· * ^ .. .k after the memory matrix; that a memory element mounted at the junction between each row line and column line of the memory matrix receives a signal on the associated line line when a lock pulse occurs on the associated column line, to the second switching stage and that in the event of an error li · n all - the memory element in the memory matrix is affected by a common closing

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via the interface in such a way that the rear second switching stages are put to sleep.

The following structural example will explain in more detail, with the aid of the drawings, a switching arrangement for implementing the method according to the invention for a time multi-channel transmission device operating according to the CEPT proposal mentioned at the beginning.

Fig. 1 shows a switching arrangement and Fig. 2 a time diagram.

The time multichannel signals transmitted in series are converted to a parallel format in a known manner, for example via a shift register SR. The binary signals of each private signaling interval are fed in parallel to the line conductors ZL of the storage matrix S, in addition to which each private signaling arrives at the line line corresponding to the internal location of the signaling interval. The number of line lines ZL of the storage matrix S thus corresponds to the number of signals transmitted for each signaling slot 3.58238 and reaches at most the number of bits transmitted in each signaling slot. Thus, the switching arrangement shown in Fig. 1 is each designed for time periods containing 8 bits, in addition, for the sake of better clarity, the reception of the first and fifth bits of each signaling time slot is shown in full. Each private signaling of the signaling time slots of one superframe structure from a given information channel is received and stored in the memory matrix S. In addition, the memory matrix S indicates the number of column lines SL depending on the number of data channels, with each column line SL and each row line ZL having a junction. Since, according to the CEPT proposal mentioned at the beginning, the signals for each signaling interval are transmitted from 2 of the 30 information channels, the memory matrix S contains a total of - 15 column lines necessary for this purpose. As a memory element in the structure example, D-

flip-flops, each of which has a D-input connected to a respective row line ZL and a CL-lock input to a respective column line SL. The power port TA in each line is further amplified by the current input signal to all the D inputs of the memory elements SE connected to the same line ZL. The locking pulse divider TV, controlled by the multiplication of the frame locking pulse RT and the phase-shifted auxiliary beat HT relative to the at least one frame locking pulse RT, always delivers the locking pulse in the same order to one column line SL after another. When such a locking pulse arrives on its respective column line SL, each memory element SE receives the signal provided to the respective row line ZL and stores it mainly until the arrival of the next locking pulse rate. The memory elements SE connected to the same column line SL in each case receive the signals of the two information channels. Thus, for example, the storage element SE connected to the column line SLI and the line line ZLI receives in each case a first signal from the signaling time slot 1 of the frame structure and the information channel 1. The memory element SE connected to the column line SL8 and the line line ZL5

on the other hand, receives in each case a fifth signal from the signaling interval of the 8th frame structure and 2k. Information from the channel.

The lock pulse divider TV used in the construction example includes two BCD decoders (binary coded decimal decoder). These are connected on the output side to the column line SL of the memory matrix S15 in such a way that during each signaling interval no frame 0 for any column line, 1st frame structure for 1st column line SLI, 2nd frame structure for 2nd column line SL2, ... etc. and 15 · In the frame structure 15.

k A locking pulse is applied to the column line 58238. The splitter of the locking pulses is controlled by the multiplication of the flkHz frame locking pulse RT, namely by synchronous, subharmonic UkHz, 2kHz, 1kHz and 0.5 kHz pulses, as well as by at least one phase shift reading of the QkHz frame locking pulse RT. The phase shift between the locking pulse HT and the frame locking pulse RT is selected so that the locking pulse rate from the respective output of the locking pulse TV arrives at the corresponding column line SL at a time when all bits of the same signaling interval ZL are available in parallel on the line lines. For each subsequent signaling interval within one frame structure, the next auxiliary lock pulse HT *, phase-shifted with respect to the frame lock pulse synchronizer RT and the previous auxiliary lock pulse HT, is required.

In this way, each private column line SL receives a locking pulse rate every 2 ms. Figure 2 shows a corresponding time diagram. -

In order to be able to switch off all memory elements SE and thus also the switched-on switching stages SA and SB in the event of an error, the additional inputs Pr of the memory elements SE of each line ZL are jointly connected to the output of the power port TB, the power port TB is connected to a common closing terminal B.

The binary signal output from the output Q of each memory element enters the first switching stage SA connected after each memory element SE via the voltage divider R1, R2 to the base of the input transistor T1 and from its collector through the second voltage divider R3, R1 to the output transistor T1 of the opposite transistor T2. The binary signal amplified by both transistors T1, T2 is received in the emitter of the output transistor T2 and fed to a second switching stage SB containing an electromagnetic relay. For this purpose, the load current applied to the output transistor T is limited by the input voltage j1, the divider R1, R2 and the common resistor RE connecting the supply voltage of the emitter of the input transistor T1 and the collector of the output transistor T2 to one terminal. As a counter-connection between the base of the input transistor T1 and the emitter of the output transistor T2, the R / C series member R, C causes the sides of the output pulse to be balanced. Thus, the higher frequency amplitudes of the output pulses are reduced, thereby reducing the risk of interference from the interference pulses of the line connecting the first switching stage SA to the second switching stage SB.

To protect the transistors T1 and T2, the induction voltages generated by the switching on and off of the electromagnetic relay located in the second switching stage SB are conducted off via the overvoltage conductors D1, Z adjacent to the output A of the switching amplifier. Zener diode Z conducts off a switching induction voltage peak greater than the switching induction voltage peak, and 5 S8238 diode D1 switches the switching induction voltage peak. One common Zener diode Z is allocated to a plurality of switch amplifiers arranged on one conductor plate, which is connected via an individual switching diode D2 to the respective switch amplifier output A and one terminal of the supply voltage.

It is self-evident that the described switching arrangement can be correspondingly applied to each desired time multi-channel device with its data transmission separated from the data transmission. Thus, the number of line lines ZL of the memory matrix S is adjustable for each signaling time interval * * · · k.

number of signals n and the number of columns in the quotient - (= number of time slots used for information channels divided by the number of information channels used for signaling in each ~ signaling slot). The number of memory elements SE to be allocated in the memory matrix S must correspond to tTolo, which consists of the number of signals transmitted to each information channel and the number of information channels.

Claims (9)

6,58238 A method for separating binary signals on the receiving side from a series of time multichannel signals, wherein in a pulse frame having a plurality of time slots, k of which are information channel time slots and at least one signaling time slot, n signals are transmitted for p information channel time slots and signals for all information channel slots signaling time slots in a superframe structure, characterized in that the signaling of each individual signaling time slot n is fed in parallel to the line matrix (ZL) of the memory matrix (S) and the phase shift of the frame lock pulse (RT) multiplier TV) gives a locking pulse to one - column line (SL) one after the other in the memory matrix P k s (S); that a memory element (SE) mounted at the intersection between each row line (ZL) and the column P line (SL) of the memory matrix (S) receives a signal from the associated column line (SL) to the associated row line (ZL) when the lock pulse occurs, temporarily stores it at the next lock pulse to the same column line (SL) and feeds it through the first switching stream (SA) behind each memory element (SE) to the second switching stage (SB) for each memory element (SE) and that in case of an error to all —— memory element (SE) in the memory matrix (S) ) is operated via a common shut-off connection (B) in such a way that the rear second switching stages (SB) are put to sleep. Connection arrangement for carrying out the method according to claim 1, characterized in that a memory matrix (S) is provided, which has at each junction 3 of the row line (ZL) and the column line (SL)? - a bistable memory element (SE) set, wherein each memory element (SE) has a first input (D) connected to the respective row line (ZL), a second input (CL) connected to the respective column line (SL) and a third input (Pr) connected to the common to the shut-off connection (B); that a locking pulse divider (TV) is further provided, which, under the control of both the multiplication of the frame locking pulse (RT) and the phase-shifted locking pulse (HT) with respect to the at least one frame locking pulse, activates the memory matrix (S) from one column line to another; and that the output (¾) of each separate k · n ^ memory element (SE) is connected to a second switching stage (SB) arranged for each memory element (SE) via its own first switching stage (SA). Switching arrangement according to Claim 2, characterized in that the bistable memory element (SE) consists of a semiconductor motion. τ 58238 1 *. Switching arrangement according to Claim 3, characterized in that each row conductor (ZL) is provided on the input side with a power port (T) for amplifying the signaling to the memory element (SE). Switching arrangement according to Claim 2, characterized in that the locking pulse divider (TV) comprises at least one BCD decoder. A switching arrangement according to claim 3, characterized in that the first switching stage (SA) is a switching amplifier comprising both an input transistor (T1) and an output transistor (T2) complementary thereto and a means for equalizing the sides of the output pulse and limiting the load current and the overvoltage on the output side. Z) to protect the transistors (T1, T2). Switching arrangement according to Claim 6, characterized in that a common overvoltage conductor (Z) is arranged for a plurality of switching amplifiers arranged on one conductor plate, which on the other hand is connected to the respective switching output (A) of the switching amplifier via a separate disconnect diode (D2). Switching arrangement according to Claim 6, characterized in that the load current limiting device consists of a common resistor (RE) connecting both the emitter of the input transistor (T1) and the collector of the output transistor (T2) and the output (Q) of the memory element (SE) and a voltage divider (R1, R2) supplying the base of the input transistor (T1) connected between the second poles of the supply voltage. Switching arrangement according to Claim 6, characterized in that an R / C series circuit (R, C) connecting the base of the input transistor (T1) to the emitter of the input transistor (T1) is provided to equalize the sides of the output pulses. A switching arrangement according to claim 2, characterized in that said second switching stage (SB) consists of an electromagnetic relay. 58238