FI57908B - KOPPLINGSANORDNING FOERSAEKRAD AVLAESNING AV IMPULSER ENLIGT DUALTALSYSTEM I DIGITALA DATABEHANDLINGSANLAEGGNINGAR SPECIELLT FOER JAERNVAEGSSAEKERHETSANLAEGGNINGAR - Google Patents

Description

ANNOUNCEMENT ISSUE

ffjBA · ™ ^ 1) UTLÄCCNINOSflCPUFT 5 790 8 C ¢ 43) Patent mySnneity 10 11 1930 Qpj Patent meddelat (51) Kv.ik.Va.3 b 61 L 25/00 // G 06? 11/30 FINLAND — FINLAND (21) ^ βΐΗΛ ^ -ρ · »« «*« βι «ΐι» ι 585/7 * + (22) Hekemltpllvl — Amttknlnptfag 27.02.7 * + (23) ΑΙΙηφΙΙν · —GlMghtadig 27.02. 7 * + (41) Interpreter JulkMcri - Bllvlt offtncilg 10.09.7 * +

Pmtmtti · Ja rckisteHhAllittit _ ............ ,. „_ _. (44) Date of first issue.

Patent- och reglsterstypetoen '' AmMun uthgd odi uti.skrHt «n pubitcw ^ d 31.07.80 (32) (33) (31) * nrf« tty utuellMU · —iugird priorltut 09.03.73

Federal Republic of Germany-Förbundsrepubliken Tyskland (DE) P 2311887.8 (71) Siemens Aktiengesellschaft, Berlin / Miinchen, DE; Wittelsbacherplatz 2, D-8000 Munchen 2, Federal Republic of Germany-Förbundsrepubliken Germany (DE) (72) Franz-Lothar Bauer, Hondelage, Federal Republic of Germany-Förbundsrepubliken

Tyskland (DE) (7 * +) Berggren Oy Ab (5 * +) Switching device for ensuring the calculation of pulses according to the dual calculation method in digital data processing plants, in particular in iron safety equipment - Kopplingsanordning för säkrad avläsning av im-pulser enligt dualtt

The invention relates to the calculation of pulses according to the dual calculation method in digital data processing plants, in particular in railway safety equipment, using two memories, each of which arithmetic calculator is connected to an "n-stage rotation register with minus again is written back to the rotation register.

Modern technology needs calculations to control the flow of the most diverse uses, for which multiplied security requirements are required for the regular determination of the calculation result. This applies, for example, especially to nuclear-physical measurements.

In railway safety equipment technology, axle counters are adapted for free and busy declarations of line sections, which are also subject to high safety requirements. These axle counters often consist in each case of a fixed line device with 2 57908 in each of at least two impulse sensors arranged in succession in the direction of travel at the beginning and end of the line section to be monitored.

The impulse sensors are acted upon successively by the vehicle axles passing the landing point and then give two pulses, which overlap in time. These are used to determine the current direction of traffic of the rail vehicle and are converted into a direction-dependent descent impulse. This shaft lowering pulse then acts as an input or output pulse for the shaft lowering device. In general, these axle counters do not need to give any absolute counting result. However, if the only landing site is required to provide the control center with precise information on the current axle number, it is very important that such axle counters do not give any axle landing values due to possible faults or similar disturbances that could lead to endangerment decisions.

The faultless design of the calculators usually requires the special manufacture of electronic components, i.e. assemblies, which require a high financial cost. If, for example, landing connections have to be installed, which have been constructed in accordance with standard TTL technology, the usual duplication of the landing equipment and the test of uniformity of operation must be used for safety reasons. In this case, however, there is always an unpleasant risk of danger, in that there are identical faults at the same point in both calculators, which are loaded in the same way, which therefore overlap and are therefore not detected.

The object of the invention is to provide a counting of pulses according to a dual calculation method, which can be implemented with normal TTL technology, using memories formed by a calculator for arithmetic operations in connection with a multi-stage rotation register. These known calculators in connection with memories are described in more detail in A.P. In Spei-ser's book "Digitale Rechenanlagen", published by Springer's publishing house in 1961, pages 179 and l80. If another number is added to the number in the memory, the number in the rotation register of the memory is read from the number of synchronous pulses and given to the arithmetic count-1 ai t.to, which, after forming the sum, stores the new, received number back in the rotation register. The corresponding course of the function is also given if the number in the memory has to be reduced by one.

3 57908 The use of these known memories as calculators in technical fields with high security requirements is not obvious, even if the two memories are matched with reference devices, as explained in more detail above, because there is still a risk of exposure.

It is therefore a further object of the invention to provide a switching device for a secure calculation so that possible identical faults in the used memories are detected in the same places in time.

To achieve this, the invention is characterized in that both rotation registers are extended by an additional step not intended for counting information, and that a special rotation register is provided with the same number of steps as the other rotation registers, which together with the memory rotation registers can be further connected in parallel, the outputs of the auxiliary stage of the register and the special rotary register are connected to an AND means for triggering the first match signal in each of the check bits of each additional stage; that the output of switching signal triggering operations is made dependent on the existence of both concatenation signals.

For example, the switching signal can be advantageously used to interpret the calculation information of one of the two memories only when the switching signal is present. However, it is also possible to maintain the synchronous power supply required for the memories only when the switching signal occurs after start-up. This advantageously ensures that in the event of an arbitrary malfunction, in which one of the two compliance signals does not come in, the memories operate in a secure manner and at most can trigger the blocking. In any case, it is essential for the idea of the invention that the additional rotation register differs from the rotation register of both memories in that this is only occupied by the check bit and not in the case of use the calculation information.

It is particularly practical and advantageous for greater certainty that additional rotation registers have been constructed by another technique in addition to memory rotation registers. In this case, the probability of two simultaneous faults in the circulating register and the compared memory circular register becomes very small, because both structural groups differ in both the information to be processed and the electronics used.

A preferred and preferred interconnection of the two match signals is achieved by a further development of the invention such that the first match signal of the AND member is applied to a descending tilt stage, the output signal of which controls the galvanically separated and DC current of the second AND member, which is further connected to the second match. with the comparator.

An example of the invention is shown in the drawing and will be explained in more detail below.

The drawing schematically shows two memories A1 and A2, each consisting of an arithmetic calculator RW1, respectively. RW2 and the multi-stage rotation register UR1 and UR2 connected after this calculator. In order to simplify the presentation, it is assumed that the rotation register UR1 and UR2 manage to store at most the occurrence calculation information on the three stages UR10, UR11 and UR12 in the rotation register UR1, respectively. UR20, UR21 and UR22 in the second rotation register UR2. Normally, both rotary registers UR1 and UR2 require significantly more stages than three. The calculation information stored in both rotary registers thus consists of three binary characters with the position valuation varying from zero to two in the duahua number system. The totality of these values - the separate binary identifiers of the stored calculation information exist in the stages UR10, UR11 and UR12 of the rotation register UR1, respectively, in the stages UR20, UR21 and UR22 of the second rotation register UR2.

An additional step UR13 is still reserved for both rotary registers UR1, UR2, respectively. UR23 not required for calculation operations.

Connectors KP1, resp. KP2 or KM1, resp. Calculators RW1, resp. RW2 decrease pulses, which are processed in the framework of addition or subtraction. Since both memories A1 and A2 represent clock-controlled calculators which, for each arithmetic calculation, require a plurality of clock pulses which coincide with the step numbers of the rotation registers UR1, respectivelyUR2, the memories A1 and A2 receive an operating clock which is imported via terminal TT. In this embodiment, it is assumed that the operating speed is independent of the fact that some descent pulses 57908 always exist. The counting information in the rotation register UR1 of the memory A1, resp. Along L2.

UR3 represents an additional rotation register with as many steps as both rotation registers UR1 and UR2. This rotation register can consist of an arbitrary ring-connected slip register, most preferably connected according to another technique, than both rotation registers UR1 and UR2. It is essential for this rotation register that there is no calculation information here, but only the check bit given via the input terminal EP2 circulates in it. The cyclic reconnection of the rotation register UR3 takes place according to the same operating rate, which also controls the memories A1 and A2. At a predetermined time, e.g. before the entire switching device is put into operation, a check bit is applied to the rotation register UR3 via the input EP2 and also a check bit via the input EP1 to the stage UR13 of the rotation register UR11.

If no counting pulse has yet been given to the rotation registers UR1 and UR2 at the time of assigning the check bit, so that the countdown pulse has a value of O, rotating taking into account the operating rate in each of the rotation registers UR1 and UR3 only one check bit.

On the output side, the rotation registers UR1 and UR3 are connected to the absolute OR element to which the comparator VR is connected. This is on one side connected to the second memory register A2 rotation UR2. An additional element UR13 and UR33 is connected to the additional stages UR13 and UR33 reserved for the outputs of the rotation registers UR1 and UR3, which controls the tilt tilt degree KE from the respective switching position to another serious position. The second output of the tilt stage KE is connected to a transformer TR adapted for galvanic isolation and a second input of a second AND member UG2 connected to the rectifier circuit GR. The second input of this logic element UG2 is connected to the output of the comparator VR, and receives a second match signal from it as long as the comparator VR receives binary signals from its inputs with a value of 0 or L.

For a more detailed explanation of the mode of operation of the switching device, it is first assumed, as above, that the rotation registers UR1 and UR2 of both memories A1 and A2 have not yet received the count information and that the check bit UR1 and UR3 of both rotation registers UR1 and UR3 are read. The check bit 5771 of the rotation register UR1 then arrives indirectly via the calculator RW1 at the stage UR13, while the check bit of the rotation register UR3 immediately arrives at the stage UR33 connected to the stage UR30. Due to the similarity of the signals at the two inputs of the absolute OR element, this gives the comparator VR a signal whose value is equal to the value of the signal given from the stage UR20 of the rotation register UR2. The comparator VR therefore determines the concordance and sends a concatenation signal to the second AND element UG2 via its second output line.

When both check bits are further connected to the rotary cistors UR1 and UR2 from stage UR13 to stage UR12, respectively, from stage UR33 to stage UR32, the AND element UG1 outputs a matching signal to the falling-tilt stage KE due to the detected signal compatibility. It is readily observed that when circulating both check bits in a continuous similar rotation in the rotation registers UR1 and UR3, i.e. in dynamic check operation without any available calculation information, a voltage is applied from the rectifier circuit GR to keep the AND element UG2 continuously ready. Since, as already briefly described, the comparator VR, in regular use of both rotation registers UR1 and UR2, also without rotating counting information, provides an active consistency signal to the AND element UG2, a switching signal is available at its output which can be used for arbitrary tripping functions, e.g. to maintain the synchronous current supply.

Assuming that neither of the two memories A1 and A2 processes the calculation information, i.e. that the double-matched calculation circuit is still in some kind of waiting state, it is once assumed that due to an error, the check bit disappears in the rotary counter UR3. This fact would be detected at the latest after one revolution of the check bit in the second rotation register UR1 by the AND element UG1 and will be reported in time at this point for the absence of the expected tripping of the consistency signal. This fault would again occur in each of the following rounds of the check bit in the rotation register UR1, so that the switching signal previously given by the AND member UG2 in the regular state of the countdown is omitted.

The same fault, i.e. the missing or faulty still connected check bit in the rotation register UR1, becomes even more pronounced in that both the consistency signal of the AND member UG1 and also the consistency signals which the comparator VR gives in regular use are missing.

7 57908

If, after the calculation of the calculation pulses, the corresponding calculation information rotates cyclically in the same way via the terminals KP1 and KP2 of both memories A1 and A2, in principle nothing changes with respect to the test operation of the U-member UG1 and the comparator VR described above. For example, if it is assumed that at a given moment both check bits are located in stages UR12 and UR32 of both rotation registers UR1 and UR3 and that further due to the assumed calculation information existing in rotation registers UR1 and UR2, UR10 and UR20 each have an L signal when reading stages UR10 and UR30 output signal, value L in comparator VR. This L signal is consistent with that given simultaneously when reading the rotation register UR1 from the stage UR10, the rotation register UR2 from the stage UR20. Thus, in this case as well, the comparator VR is provided with signals whose values are the same, so that in this case too a corresponding signal is given to the AND element UG2, so that no interruption occurs to the switching signal given by it.

In a preferred manner, the calculation information provided from the memory A1 is used further. The reason for this is that the disturbance of the memory A1 can be detected independently of the given calculation information, whereas this is true of the memory A2 only when the calculation information given by the calculating device RW2 to the rotation register UR2 rotates.

Claims (4)

8 57908 1. Switching device for ensuring the calculation of pulses according to the dual calculation method in digital data processing facilities, in particular railway safety equipment, using two memories, each of which arithmetic calculator is connected to an n-stage rotation register again written back to the rotation register, characterized in that both rotation registers (UR1, UR2) are expanded by an additional step (UR13, UR23) not intended for counting information, and that a special rotation register (UR3) is provided with the same number of steps as both other rotation registers , UR2), which together with the rotation registers (UR1, UR2) of the memories (A1, A2) can be further connected in parallel to the additional stage (UR13, respectively UR33) of the second rotation register (UR1) and the special rotation register (UR33). UR3) outputs are connected to an AND (UG1) to trigger the first match signal in each of the check bits of each of the two additional stages (UR13, UR33), so that the outputs of the rotation registers (UR1, UR3) are connected to the check bit by an absolute OR (EOD) The (UR2) output is connected to a comparator (YR) for the second concatenation signal, the values of the output signals being concordant and that the output of the triggering measures of the switching signal is made dependent on the existence of both concatenation signals. Switching device according to claim 1, characterized in that the first matching signal of the AND member (UG1) is applied to a decreasing tilt stage (KE), the output signal of which controls the second AND member (UG2) galvanically isolated and in direct current, which is further connected to a comparator providing a second matching signal. with. 1. A copy of the data transmission system with an impulse system or digital data processing system, specially adapted for the purpose of transmitting data, under the same information as the data transmission system, for example, an arithmetic network device for the arithmetic network. under behandling av en talimpuls utläses efter n