FI54752C - Buffertminnesanordning foer att i en datamaskinstyrd telekommunikationsanlaeggning aostadkomma en foerdroejd adressering - Google Patents

Buffertminnesanordning foer att i en datamaskinstyrd telekommunikationsanlaeggning aostadkomma en foerdroejd adressering

Info

Publication number
FI54752C
FI54752C FI347/70A FI34770A FI54752C FI 54752 C FI54752 C FI 54752C FI 347/70 A FI347/70 A FI 347/70A FI 34770 A FI34770 A FI 34770A FI 54752 C FI54752 C FI 54752C
Authority
FI
Finland
Prior art keywords
telekommunikationsanlaeggning
foerdroejd
datamaskinstyrd
buffertminnesanordning
adressering
Prior art date
Application number
FI347/70A
Other languages
English (en)
Other versions
FI54752B (fi
Inventor
Goeran Anders Henrik Hemdal
Nils Bertil Lennmarker
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of FI54752B publication Critical patent/FI54752B/fi
Application granted granted Critical
Publication of FI54752C publication Critical patent/FI54752C/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
FI347/70A 1969-02-18 1970-02-09 Buffertminnesanordning foer att i en datamaskinstyrd telekommunikationsanlaeggning aostadkomma en foerdroejd adressering FI54752C (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE02240/69A SE328918B (fi) 1969-02-18 1969-02-18

Publications (2)

Publication Number Publication Date
FI54752B FI54752B (fi) 1978-10-31
FI54752C true FI54752C (fi) 1979-02-12

Family

ID=20259609

Family Applications (1)

Application Number Title Priority Date Filing Date
FI347/70A FI54752C (fi) 1969-02-18 1970-02-09 Buffertminnesanordning foer att i en datamaskinstyrd telekommunikationsanlaeggning aostadkomma en foerdroejd adressering

Country Status (11)

Country Link
US (1) US3644895A (fi)
JP (1) JPS5220811B1 (fi)
BE (1) BE746140A (fi)
DK (1) DK123955B (fi)
FI (1) FI54752C (fi)
FR (1) FR2035563A5 (fi)
GB (1) GB1285656A (fi)
NL (1) NL7002190A (fi)
NO (1) NO121790B (fi)
SE (1) SE328918B (fi)
SU (1) SU362551A3 (fi)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3927394A (en) * 1972-02-29 1975-12-16 Nippon Steel Corp Control system for computer use for on-line control
FR2188884A5 (fi) * 1972-06-15 1974-01-18 Jeumont Schneider
US3969703A (en) * 1973-10-19 1976-07-13 Ball Corporation Programmable automatic controller
US4270185A (en) * 1977-06-20 1981-05-26 Motorola Israel Limited Memory control circuitry for a supervisory control system
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
DE3507326A1 (de) * 1985-03-01 1986-09-04 Siemens AG, 1000 Berlin und 8000 München Anordnung zur zeitverzoegerten weiterleitung von seriell auftretenden digitalen datenfolgen
DE60025435T2 (de) * 1999-09-13 2006-09-21 Nippon Telegraph And Telephone Corp. Parallelverarbeitungsvorrichtung und -verfahren
US20020187446A1 (en) * 2001-06-07 2002-12-12 Wong Chi Lam Torch lighter for cigar
US20040249997A1 (en) * 2003-02-26 2004-12-09 Umberhocker Richard B. System and method for communicating data

Also Published As

Publication number Publication date
FI54752B (fi) 1978-10-31
DK123955B (da) 1972-08-21
BE746140A (fr) 1970-07-31
US3644895A (en) 1972-02-22
NO121790B (fi) 1971-04-13
JPS5220811B1 (fi) 1977-06-06
DE2007401B2 (de) 1973-01-04
NL7002190A (fi) 1970-08-20
FR2035563A5 (fi) 1970-12-18
DE2007401A1 (de) 1970-08-20
SE328918B (fi) 1970-09-28
GB1285656A (en) 1972-08-16
SU362551A3 (fi) 1972-12-13

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